Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored Contributor1) you can't do that with just VHDL. You need an external ADC chip.
2) it depends on how you coded your process. Having both rising and falling edges conditions in the same process can produce that error.
