Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored ContributorThe frequency variations will be very low. To get exact pwm with reference to the input , pll is needed.
I just want to know how to convert my analog input to digital . it can be implemented only vhdl code or any other inbuilt adc is available in altera fpga. Your help is really appreciated
