Altera_Forum
Honored Contributor
Honored ContributorPhase lock loop
I want to implement a phase lock loop in fpga , altera(cyclone II). The internal clock is 50 MHZ. but my input clock is 60 HZ. How i should implement pll in this case???
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Altera_ForumHonored Contributor
Honored ContributorSince my input is in 60 Hz will below PDF block diagram works for me to get synchronization of the input.
http://users.ece.gatech.edu/~jskenney/l080-adpll(2up).pdf (http://users.ece.gatech.edu/%7ejskenney/l080-adpll%282up%29.pdf) file:///C:/DOCUME%7E1/kvvani/LOCALS%7E1/Temp/moz-screenshot.jpg In attached pdf on (page file:///C:/DOCUME%7E1/kvvani/LOCALS%7E1/Temp/moz-screenshot-1.jpg 080-18) example 1 . Kindly help me
