How to constraint max skew between two net or balance the delay between two net?

Hi Nurina

Thank you, Nurina, very much.

The path1 is from PAD1 to clock_a of module A.

The path2 is from PAD2 to data_a of module A. The data_a is one bit data.

I hadn't tried to separate constraint. I will try it. And how to report the skew between those two paths?

I'm confused that separating the constraint can balance those two paths?

Those two paths aren't in the same group like data bus, data[7:0].

I'm confusing how to balance the delay of those two paths.

Thank you very much

Hi Nurina

Thank you, Nurina, very much.

The design is as follow picture.

PAD1 is used as a clock of module A.

PAD2 is used as a data of module A. And PAD have a multi function. It uses PAD2 as a clock of module B.

Some flipflop in the module A use data_a as a clock.

So, I create a clock on node data_a.

I don't want to create a clock for data_a on PAD2 because it will cause many false paths.

Due to that, I constraint data_a on the node data_a of module A.

Clock domain data_a and Clock domain clock_a have data crossing.

So, the clock from the data_a and the clock from clock_a is in the same clock group.

(Designer tell me that clock domain data_a and clock domain clock_a should be in the same clock group.)

The detail of constraint of the design is as follow.

Design:

Constraint example:

create_clock clock_a [get_port Module_A|clock_a]

create_clock data_a [get_port Module_A|data_a]

create_clock clock_b [get_port Module_B|clock_a]

create_clock_groups -asynchronous -group [clock_b ]

-group [clock_a data_a]

After Fitter, the net from PAD1 to clock_a and net from PAD2 to data_a become as follow picture.

The delay of the path from PAD1 to clock_a (Path1) and the path from PAD2 to data_a (Path2) is unconstrainted.

I add the constraint as follow for these two path.

Constraint:

set_net_delay -max 5.0 -from PAD1 to clock_a

set_net_delay -min 0.0 -from PAD1 to clock_a

set_net_delay -max 5.0 -from PAD1 to data_a

set_net_delay -min 0.0 -from PAD1 to data_a

And I want to balance the delay between the path from PAD1 to clock_a (Path1) and the path from PAD2 to data_a (Path1) for the min clock skew between clock domain clock_a and clock domain data_a.

But I'm confused how to minimize the clock skew.

The one way I think is to balance the skew of these two paths.

Then I'm confused how to balance the skew of these two paths.

Hi Nurina

Thank you, Nurina, very much.

Yes, to is a typo.

And how to constraint the path from PAD1 to clock_a (Path1) and the path from PAD2 to data_a (Path2)?

Path1 and Path2 aren't a grouped paths, like R2 to R3 in the video.

I had tried following constraint. But "report_max_skew" command don't report any path.

Constraint:

set_max_skew 1.0 -from [get_ports {PAD1 PAD2}] \

-to [get_nets {A|clock_a A|data_a}]]

Hi Nurina

Thank you, Nurina, very much.

I can't see the picture. And sorry that I didn't quite catch your point.

Where are the R1 and R2 in my design?

I can't find any register (R1, R2) on the path from PAD1 to clock_a (Path1) and the path from PAD2 to data_a (Path2).

Thank you very much.

Hi Nurina

Thank you, Nurina, very much.

Data_a and Clock_a are in the same clock domain. So, R1 and R2 should meet the setup and hold timing.

If I constraint the skew between R1 and R2 on the previous picture, how to know the path delay (PAD1 to Clock_a, PAD2 to Data_a) meet the requirement?

I only constraint the net delay as follows on the paths which are from PAD1 to Clock_a and from PAD2 to Data_a.

Constraint:

set_net_delay -max 5.0 -from PAD1 -to clock_a

set_net_delay -min 0.0 -from PAD1 -to clock_a

set_net_delay -max 5.0 -from PAD2 -to data_a

set_net_delay -min 0.0 -from PAD2 -to data_a

Hi AEsqu

Thank you, AEsqu, very much.

The design and the constraint are as follows.

If I use set_min_delay and set_max_delay on the ports, how to report timing report?

Sorry that I have no experience about reporting set_min_delay and set_max_delay constraint on the paths (PAD1 to Clock_a, PAD2 to Data_a).

I only know how to report setup, hold, recovery, removal, and skew in TimeQuest.

Design:

Constraint:

create_clock Clock_a [get_port Module_A|Clock_a]

create_clock Data_a [get_port Module_A|Data_a]

create_clock Clock_b [get_port Module_B|Clock_a]

create_clock_groups -asynchronous -group [Clock_b ]

-group [Clock_a Data_a]

set_net_delay -max 5.0 -from PAD1 -to Clock_a

set_net_delay -min 0.0 -from PAD1 -to Clock_a

set_net_delay -max 5.0 -from PAD2 -to Data_a

set_net_delay -min 0.0 -from PAD2 -to Data_a

Hi AEsqu

Thank you, AEsqu, very much.

Recently, I get an information that both set_min_delay and set_max_delay only work on the path which has setup/hold relationship.

Could you please tell me how you to constraint your clock or constraint the setup/hold relationship.

Thank you very much.

Hi Nurina

Thank you, Nurina, very much. I will see it. Thank you very much.

Hi Nurina

Thank you, Nurina, very much. OK. Thank you very much.