ContributorHello,
You may refer to this video on how to constraint your design: https://www.youtube.com/watch?v=ggWxledaBFg
Regards,
Nurina
ContributorHi AEsqu
Thank you, AEsqu, very much.
The design and the constraint are as follows.
If I use set_min_delay and set_max_delay on the ports, how to report timing report?
Sorry that I have no experience about reporting set_min_delay and set_max_delay constraint on the paths (PAD1 to Clock_a, PAD2 to Data_a).
I only know how to report setup, hold, recovery, removal, and skew in TimeQuest.
Design:
Constraint:
create_clock Clock_a [get_port Module_A|Clock_a]
create_clock Data_a [get_port Module_A|Data_a]
create_clock Clock_b [get_port Module_B|Clock_a]
create_clock_groups -asynchronous -group [Clock_b ]
-group [Clock_a Data_a]
set_net_delay -max 5.0 -from PAD1 -to Clock_a
set_net_delay -min 0.0 -from PAD1 -to Clock_a
set_net_delay -max 5.0 -from PAD2 -to Data_a
set_net_delay -min 0.0 -from PAD2 -to Data_a
ContributorTry with report path from the GUI (Quartus 22.1.0)
Example:
report_path -from [get_ports {IO1_SWM10}] -npaths 100 -panel_name {Report Path} -multi_corner
ContributorHi AEsqu
Thank you, AEsqu, very much.
I will try it. Thank you very much.
Before that, I have two questions in follows.
(1)Do I need manually report the path every time after compiling done to check that the path timing is correct?
(2)If I use set_min_delay and set_max_delay on the ports, how to know that the min delay value and the max delay value make sense?
For example, as follows constraints, both case(1) and case(2) limit the max skew to 1 ns.
But which case make sense more?
Constraints:
case(1):
set_max_delay 5.0 -from PAD1 -to Clock_a
set_min_delay 4.0 -from PAD1 -to Clock_a
set_max_delay 5.0 -from PAD2 -to Data_a
set_min_delay 4.0 -from PAD2 -to Data_a
case(2):
set_max_delay 100.0 -from PAD1 -to Clock_a
set_min_delay 99.0 -from PAD1 -to Clock_a
set_max_delay 100.0 -from PAD2 -to Data_a
set_min_delay 99.0 -from PAD2 -to Data_a
