timing violation fix

hi,   I am working on the project that base on agilex 7 fpga. 

project background:

1. the compile setting is superior performance, sys clock is 416Mhz
2. the ALM resources of the project has occupied the 70%,  and  has WNS -0.9 ns, TNS -29ooo ns violation.   

do you have better metholodgies for timing fix？ 

now my work flow:

1. first analyze the fit.retiming.rpt and fit.fastforward.rpt, add pipe or register according to critical chain reported in the retiming.rpt,
2. then start to next compile

I doesn't analyze the fit.timing.rpt,  because the endpoint is too large, and the work efficiency is low