Using Reset Release IP (Agilex, Stratix) without IP catalog via simple instantiation is ok?

Anything against using the reset release IP without going the IP catalog -> Platform Designer way bey simply:

-- library clause to make the altera library containing
-- the internal implementation of reset release IP visible
library altera_s10_user_rst_clkgate_1949;
...

entity...
  ...
end entity;

architecture ...

  -- declaring the component for VHDL fitting the internal
  -- reset release IP (name and port naming have to fit 
  -- for VHDL default binding)
  component altera_s10_user_rst_clkgate is
    port (
      ninit_done : out std_logic -- ninit_done
    );
  end component altera_s10_user_rst_clkgate;

  signal nInitDone : std_ulogic;

begin

  -- instantiation of the reset release IP
  TheResetRelease : component altera_s10_user_rst_clkgate
    port map (
      ninit_done => nInitDone  -- ninit_done.reset);

  -- combine the asynchronous reset signal combinatorially with the
  -- nInitDone signal in the further code

  ...

end architecture Rtl;

This would speed up things and has improved readability also.

If it is not ok, please give concrete reasons speaking against this approach.