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NuvKFC's avatar
NuvKFC
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3 years ago
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How to constraint max skew between two net or balance the delay between two net?

I have two end point (two path) that need to balance the delay. The design is as follows. Path1: PAD1-->clock of module A: clock_a Path2: PAD2-->data of module A: data_a How t...
AEsqu's avatar
AEsqu
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3 years ago

For my use case where I was playing with set_min_delay and set_max_delay

is where I was bringing a clock out from the FPGA towards a pin, that was used by another Chip.

I made sure that the clock rising edge occured after the DATA outputs were already stable.

So I added a bit more delay on the clk output compare to the data output and that was working fine (the data outputs were driven by the FPGA on the same internal clk).

Example:

   set RF_SPI_CLK_MIN_DELAY 7.0
   set RF_SPI_CLK_MAX_DELAY 11.0
   set RF_SPI_EXTRA_MIN_DELAY   [expr {$RF_SPI_CLK_MIN_DELAY+5.0}]
   set RF_SPI_EXTRA_MAX_DELAY   [expr {$RF_SPI_CLK_MAX_DELAY+5.0}]
   
   set_min_delay -to $rf_spi_clk_port $RF_SPI_CLK_MIN_DELAY
   set_max_delay -to $rf_spi_clk_port $RF_SPI_CLK_MAX_DELAY
   
   set_min_delay -to $rf_spi_mosi_port $RF_SPI_EXTRA_MIN_DELAY
   set_max_delay -to $rf_spi_mosi_port $RF_SPI_EXTRA_MAX_DELAY
   
   set_min_delay -to $rf_spi_cs_n_port $RF_SPI_EXTRA_MIN_DELAY
   set_max_delay -to $rf_spi_cs_n_port $RF_SPI_EXTRA_MAX_DELAY
   
   set_min_delay -from $rf_spi_miso_port $RF_SPI_EXTRA_MIN_DELAY
   set_max_delay -from $rf_spi_miso_port $RF_SPI_EXTRA_MAX_DELAY
  • NuvKFC's avatar
    NuvKFC
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    3 years ago

    Hi AEsqu

    Thank you, AEsqu, very much.

    Recently, I get an information that both set_min_delay and set_max_delay only work on the path which has setup/hold relationship.

    Could you please tell me how you to constraint your clock or constraint the setup/hold relationship.

    Thank you very much.