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Nurina
Regular Contributor
3 years agoSorry about that. Let me try to re-upload it.
NuvKFC
Contributor
3 years agoHi Nurina
Thank you, Nurina, very much.
Data_a and Clock_a are in the same clock domain. So, R1 and R2 should meet the setup and hold timing.
If I constraint the skew between R1 and R2 on the previous picture, how to know the path delay (PAD1 to Clock_a, PAD2 to Data_a) meet the requirement?
I only constraint the net delay as follows on the paths which are from PAD1 to Clock_a and from PAD2 to Data_a.
Constraint:
set_net_delay -max 5.0 -from PAD1 -to clock_a
set_net_delay -min 0.0 -from PAD1 -to clock_a
set_net_delay -max 5.0 -from PAD2 -to data_a
set_net_delay -min 0.0 -from PAD2 -to data_a