Forum Discussion
You can try using set_min_delay / set_max_delay instead on the ports
Hi AEsqu
Thank you, AEsqu, very much.
The design and the constraint are as follows.
If I use set_min_delay and set_max_delay on the ports, how to report timing report?
Sorry that I have no experience about reporting set_min_delay and set_max_delay constraint on the paths (PAD1 to Clock_a, PAD2 to Data_a).
I only know how to report setup, hold, recovery, removal, and skew in TimeQuest.
Design:
Constraint:
create_clock Clock_a [get_port Module_A|Clock_a]
create_clock Data_a [get_port Module_A|Data_a]
create_clock Clock_b [get_port Module_B|Clock_a]
create_clock_groups -asynchronous -group [Clock_b ]
-group [Clock_a Data_a]
set_net_delay -max 5.0 -from PAD1 -to Clock_a
set_net_delay -min 0.0 -from PAD1 -to Clock_a
set_net_delay -max 5.0 -from PAD2 -to Data_a
set_net_delay -min 0.0 -from PAD2 -to Data_a