How to constraint max skew between two net or balance the delay between two net?

Hi Nurina

Thank you, Nurina, very much.

The design is as follow picture.

PAD1 is used as a clock of module A.

PAD2 is used as a data of module A. And PAD have a multi function. It uses PAD2 as a clock of module B.

Some flipflop in the module A use data_a as a clock.

So, I create a clock on node data_a.

I don't want to create a clock for data_a on PAD2 because it will cause many false paths.

Due to that, I constraint data_a on the node data_a of module A.

Clock domain data_a and Clock domain clock_a have data crossing.

So, the clock from the data_a and the clock from clock_a is in the same clock group.

(Designer tell me that clock domain data_a and clock domain clock_a should be in the same clock group.)

The detail of constraint of the design is as follow.

Design:

Constraint example:

create_clock clock_a [get_port Module_A|clock_a]

create_clock data_a [get_port Module_A|data_a]

create_clock clock_b [get_port Module_B|clock_a]

create_clock_groups -asynchronous -group [clock_b ]

-group [clock_a data_a]

After Fitter, the net from PAD1 to clock_a and net from PAD2 to data_a become as follow picture.

The delay of the path from PAD1 to clock_a (Path1) and the path from PAD2 to data_a (Path2) is unconstrainted.

I add the constraint as follow for these two path.

Constraint:

set_net_delay -max 5.0 -from PAD1 to clock_a

set_net_delay -min 0.0 -from PAD1 to clock_a

set_net_delay -max 5.0 -from PAD1 to data_a

set_net_delay -min 0.0 -from PAD1 to data_a

And I want to balance the delay between the path from PAD1 to clock_a (Path1) and the path from PAD2 to data_a (Path1) for the min clock skew between clock domain clock_a and clock domain data_a.

But I'm confused how to minimize the clock skew.

The one way I think is to balance the skew of these two paths.

Then I'm confused how to balance the skew of these two paths.