CYCLONE IVE ODDR delay mismatch

Hello Altera Experts!

I am using Quartus Standard 24.1..

I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultaneously. 9 of the 10 bits are aligned, while one has an additional delay of about 2 nsec.

I created two 10-bit buses (to drive two DACs), and the strange thing is that bit (3) is always delayed on both buses.

I'm attaching the project, hoping some experts can help me.

The ddr registers are correctly instantiated, but in the timing analysis, the bit(3) coming out of the fpga is delayed compared to all the others:

TIMING ON BUS_A:

TIMING ON BUS_B:

REGULAR DELAY:

BIG DELAY:

The only difference I see is that the "slow" pins are both also Vrefs (pin 105 and pin 80):

Could this be the reason?

regards,

LUCA.