Constraint for phase-shifted external clock (Specifying Clock Waveform Edges)

With those fractional frequencies, I don't think the two clocks are exactly synchronous to each other, so they are going to line up at some point, which the timing analyzer is pointing out.

3.571 x 4 = 14.284 < 14.286

How is the hold slack with the same timing path? If the hold has enough window, perhaps you can use set_min_delay sdc constraint to the path.

Could you please share your design by archiving the project (Project > Archive Project) so that I can investigate it further?

Regards,

Richard Tan

The frequencies have to be exact multiples of each other. Even in that hold timing analysis that is passing, the clock edges are incorrect compared to your diagram up top, further proving what I was saying.

Like I said, you're using decimal frequencies/phase shifts that are not exactly multiples of each other in your constraints. Why can't they be:

create_clock -name ADC_DCO -period 14.286 -waveform {0 7.142} [get_ports {ADC_DCO ADC_DCO(n)}]
create_clock -name ADC_FCO -period 100 -waveform {3.571 53.571} [get_ports {ADC_FCO ADC_FCO(n)}]

Better yet, input one clock and use a PLL to generate the 2 synchronous clocks if you can.

These are very odd frequencies and phase shifts to rely on just what is arriving at the device.

You can try to add set_multicycle_path constraint for fast-to-slow clock.

multicycle -setup with a value of N, and a multicycle -hold with a value of N-1

set_multicycle_path N -setup -from launch_clk(fast) -to latch_clock(slow) -start 
set_multicycle_path N-1 -hold -from launch_clk(fast) -to latch_clock(slow) 

Regards,

Richard Tan

My bad, I noticed the hold is -end instead of -start. FYI we use -end for both setup and hold, for slow-to-fast clock.

Use these constraints instead.

set_multicycle_path N -setup -from launch_clk(fast) -to latch_clock(slow) -start 

set_multicycle_path N-1 -hold -from launch_clk(fast) -to latch_clock(slow) -start

Regards,

Richard Tan

I think I might have misunderstood your question regarding how to phase shift the clock. Initially, I was focused on closing the design timing.

The recommended solution is to first reconfigurable your IOPLL, then use dynamic phase shift to achieve the phase shift you want.

Please refer to this UG. Section 2.3.11.3. Programmable Phase Shift

https://cdrdv2-public.intel.com/666937/ug_m10_clkpll-683047-666937.pdf

Regards,

Richard Tan

Dropping a note to ask if my last reply was helpful to you?

Do you need any further assistance from my side?

Regards,

Richard Tan

Since these clocks are external clock, use create_clock (without the -target), to add a virtual clock for the I/O interface.

example: create_clock -period 5.0 -name dac_clk_ext

Note that I did not apply these clocks to anything in the FPGA, which is what makes them virtual clocks; they exist outside of the FPGA.

Manually phase-shifting a clock, usually done with a PLL. Try to use the create_generated_clock so that the generated clocks are related, so crossings between them are not asynchronous.

# Create a virtual clock, and two generated clocks that derive from it.

# This makes the generated clocks related, so crossings between them are not asynchronous.

create_clock -period 10 -name virtual_base

create_generated_clock -master_clock virtual_base -divide_by 2 [get_ports clka]

create_generated_clock -master_clock virtual_base -divide_by 4 [get_ports clkb]

Reference: https://www.intel.com/content/www/us/en/docs/programmable/683432/22-1/tcl_pkg_sdc_ver_1-5_cmd_create_generated_clock.html

As mentioned by Sstrell in the previous post, the frequencies have to be exact multiples of each other.

Regards,

Richard Tan

In your case, I believe it is recommended to multiply by an integer instead, as it will meet your requirement of ensuring the clocks are phase-shifted.

If not using an exact multiplier, the phase shift difference will either get closer or further away, eventually not meeting the desired phase shift.

Sorry for the confusion, may I know is the clock constrained is inside the FPGA or outside the FPGA?

Regards,

Richard Tan