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HKana17's avatar
HKana17
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Constraint for phase-shifted external clock (Specifying Clock Waveform Edges)

Hi, I have a project in which MAX10 has an external ADC that has LVDS connections-- data, ADC_DCO, ADC_FCO. I wrote a constraint for external clocks like the next picture, but Timing Analyzer doe...
Timing
  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    After looking at the Board Configuration, I believe this is Source-Synchronous Interface.

    You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.

    Link: https://www.intel.com/content/www/us/en/content-details/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces.html

    With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.


    One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.


    Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

How is the hold slack with the same timing path? If the hold has enough window, perhaps you can use set_min_delay sdc constraint to the path.

Could you please share your design by archiving the project (Project > Archive Project) so that I can investigate it further?

Regards,

Richard Tan

  • HKana17's avatar
    HKana17
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Guys, thank you for your reply.
    And nice to see you again.

    Here is the hold time slack on the same path. It is 1.040 ns.

    I can't disclose the whole project file because I am developing this with my customer.

    ADC_FCO clock is the timing frame signal of the ADC. So ADC_DCO clock and ADC_FCO clock are synchronized. How can I tell Timing Analyzer these kinds of clocks?

    Best regards,

    HKana17