Forum Discussion
Occasional ContributorConstraint for phase-shifted external clock (Specifying Clock Waveform Edges)
After looking at the Board Configuration, I believe this is Source-Synchronous Interface.
You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.
With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.
One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.
Regards,
Richard Tan
Super ContributorIn your case, I believe it is recommended to multiply by an integer instead, as it will meet your requirement of ensuring the clocks are phase-shifted.
If not using an exact multiplier, the phase shift difference will either get closer or further away, eventually not meeting the desired phase shift.
Sorry for the confusion, may I know is the clock constrained is inside the FPGA or outside the FPGA?
Regards,
Richard Tan
HKana17Thank you for your comments.
Here is the configuration drawing.
I mean constraints for circuits on MAX10 inside. Suppose that traces from the ADC to MAX10 are the same length.
