Forum Discussion
Occasional ContributorConstraint for phase-shifted external clock (Specifying Clock Waveform Edges)
After looking at the Board Configuration, I believe this is Source-Synchronous Interface.
You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.
With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.
One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.
Regards,
Richard Tan
Super ContributorAfter looking at the Board Configuration, I believe this is Source-Synchronous Interface.
You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.
With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.
One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.
Regards,
Richard Tan
HKana17Thank you for your comments.
I didn't know that kind of configuration name, Source-Synchronous Interfaces.
I see AN433 for the first time. It has many contents, so I would like to take the time to check it.
I will close this case. For another question, I will create a new case.
Thank you again.
HKana17
muhammadhammaf2424New Contributor
<p>After looking at the Board Configuration, I believe this is Source-Synchronous Interface.</p>
<p>You may refer to the <a href="https://www.intel.com/content/www/us/en/content-details/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces.html">AN 433: Constraining and Analyzing Source-Synchronous Interfaces</a>, section "Input Clock Constraints" on how to constrain the clock.</p>
<p>With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.</p>
<p>One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.</p>
<p>Regards,</p>
<p>Richard Tan</p>
