Forum Discussion
Occasional ContributorConstraint for phase-shifted external clock (Specifying Clock Waveform Edges)
After looking at the Board Configuration, I believe this is Source-Synchronous Interface.
You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.
With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.
One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.
Regards,
Richard Tan
Super ContributorThe frequencies have to be exact multiples of each other. Even in that hold timing analysis that is passing, the clock edges are incorrect compared to your diagram up top, further proving what I was saying.
HKana17Thank you for your reply.
Do you mean using the "-divide_by" or "-multiply_by" option for external clocks? I think they are for generated clocks or internal PLL clocks...
How can I write a constraint for external clocks synchronized with each other in my case? I saw "Intel Quartus Prime Timing Analyzer Cookbook" before making a question.
Best regards,
HKana17
