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HKana17's avatar
HKana17
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Constraint for phase-shifted external clock (Specifying Clock Waveform Edges)

Hi, I have a project in which MAX10 has an external ADC that has LVDS connections-- data, ADC_DCO, ADC_FCO. I wrote a constraint for external clocks like the next picture, but Timing Analyzer doe...
Timing
  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    After looking at the Board Configuration, I believe this is Source-Synchronous Interface.

    You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.

    Link: https://www.intel.com/content/www/us/en/content-details/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces.html

    With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.


    One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.


    Regards,

    Richard Tan


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

The frequencies have to be exact multiples of each other. Even in that hold timing analysis that is passing, the clock edges are incorrect compared to your diagram up top, further proving what I was saying.

  • HKana17's avatar
    HKana17
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Thank you for your reply.

    Do you mean using the "-divide_by" or "-multiply_by" option for external clocks? I think they are for generated clocks or internal PLL clocks...

    How can I write a constraint for external clocks synchronized with each other in my case? I saw "Intel Quartus Prime Timing Analyzer Cookbook" before making a question.

    Best regards,

    HKana17