Forum Discussion
Occasional ContributorConstraint for phase-shifted external clock (Specifying Clock Waveform Edges)
After looking at the Board Configuration, I believe this is Source-Synchronous Interface.
You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.
With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.
One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.
Regards,
Richard Tan
Super ContributorDropping a note to ask if my last reply was helpful to you?
Do you need any further assistance from my side?
Regards,
Richard Tan
Occasional ContributorThank you for your comments. But my question isn't solved. The question is how to make a constraint for external clocks (ADC_DCO & ADC_FCO) provided by an external ADC. Their phase is precisely as described in the ADC timing chart of the datasheet (I gave the timing chart before.).
I will add some supplement explanations to the first post later.
Regards,
HKana17
