Forum Discussion

HKana17's avatar
HKana17
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Constraint for phase-shifted external clock (Specifying Clock Waveform Edges)

Hi, I have a project in which MAX10 has an external ADC that has LVDS connections-- data, ADC_DCO, ADC_FCO. I wrote a constraint for external clocks like the next picture, but Timing Analyzer doe...
Timing
  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    After looking at the Board Configuration, I believe this is Source-Synchronous Interface.

    You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.

    Link: https://www.intel.com/content/www/us/en/content-details/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces.html

    With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.


    One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.


    Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Dropping a note to ask if my last reply was helpful to you?

Do you need any further assistance from my side?


Regards,

Richard Tan


HKana17's avatar
HKana17
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Thank you for your comments. But my question isn't solved. The question is how to make a constraint for external clocks (ADC_DCO & ADC_FCO) provided by an external ADC. Their phase is precisely as described in the ADC timing chart of the datasheet (I gave the timing chart before.).


I will add some supplement explanations to the first post later.

Regards,

HKana17