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HKana17's avatar
HKana17
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
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Constraint for phase-shifted external clock (Specifying Clock Waveform Edges)

Hi, I have a project in which MAX10 has an external ADC that has LVDS connections-- data, ADC_DCO, ADC_FCO. I wrote a constraint for external clocks like the next picture, but Timing Analyzer doe...
Timing
  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    After looking at the Board Configuration, I believe this is Source-Synchronous Interface.

    You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.

    Link: https://www.intel.com/content/www/us/en/content-details/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces.html

    With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.


    One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.


    Regards,

    Richard Tan


RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

My bad, I noticed the hold is -end instead of -start. FYI we use -end for both setup and hold, for slow-to-fast clock.

Use these constraints instead.

set_multicycle_path N -setup -from launch_clk(fast) -to latch_clock(slow) -start 

set_multicycle_path N-1 -hold -from launch_clk(fast) -to latch_clock(slow) -start

Regards,

Richard Tan

  • HKana17's avatar
    HKana17
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Thank you for your suggestion. I added -start option. The hold-time timing chart varied. But the rising edge of 2 waveforms is still at the same time. I think it is necessary to shift the edge time between 2 signals rather than the multiplier factor.


    And I don't know the set_multicycle_path option well. Do you know a good text of a sdc file grammar?

    Regards,

    HKana17