Constraint for phase-shifted external clock (Specifying Clock Waveform Edges)

Hi, I have a project in which MAX10 has an external ADC that has LVDS connections-- data, ADC_DCO, ADC_FCO. I wrote a constraint for external clocks like the next picture, but Timing Analyzer doe...

Timing

RichardT_altera
2 years ago
After looking at the Board Configuration, I believe this is Source-Synchronous Interface.
You may refer to the AN 433: Constraining and Analyzing Source-Synchronous Interfaces, section "Input Clock Constraints" on how to constraint the clock.
Link: https://www.intel.com/content/www/us/en/content-details/653688/an-433-constraining-and-analyzing-source-synchronous-interfaces.html
With the current clock constraints you have, they are not synchronous with each other. Therefore, meeting either the phase-shift or frequency requirement cannot fulfill both requirements simultaneously.

One approach I can suggest is to write a clock constraint in such a way that Quartus treats this as a PLL, ensuring that both clocks are synchronous with each other.

Regards,
Richard Tan

RichardT_altera

Super Contributor

2 years ago

You can try to add set_multicycle_path constraint for fast-to-slow clock.

multicycle -setup with a value of N, and a multicycle -hold with a value of N-1

set_multicycle_path N -setup -from launch_clk(fast) -to latch_clock(slow) -start 
set_multicycle_path N-1 -hold -from launch_clk(fast) -to latch_clock(slow)

Regards,

Richard Tan