Clock missing from Timing Analyzer - Report Setup Summary

Hi,

If create the clock in the timing analyzer, and use the auto-generated .sdc. Will it reflected?

Thanks,

Regards,

Sheng

Many thanks for your reply.

Second attempt at posting!

I haven't made any changes to the Assignment Editor, but deleted/renamed the old sdc file and created a new one from Timing Analyzer.

These are now the active lines in the sdc file:

**************************************************************

create_clock -name {altera_reserved_tck} -period 33.333 -waveform { 0.000 16.666 } [get_ports {altera_reserved_tck}]
create_clock -name {HDMI_TX_CLK} -period 6.750 -waveform { 0.000 3.375 } [get_ports {HDMI_TX_CLK}]

set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -rise_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -rise_to [get_clocks {altera_reserved_tck}] -hold 0.270
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -setup 0.280
set_clock_uncertainty -fall_from [get_clocks {altera_reserved_tck}] -fall_to [get_clocks {altera_reserved_tck}] -hold 0.270

set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]

set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_ed9:dffpipe15|dffe16a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_dd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_hd9:dffpipe19|dffe20a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_gd9:dffpipe13|dffe14a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_rd9:dffpipe8|dffe9a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_qd9:dffpipe5|dffe6a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_pd9:dffpipe8|dffe9a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_od9:dffpipe5|dffe6a*}]

**************************************************************

After compiling the design which fitted fine and very quickly, I reopened Timing Analyzer, "Read the SDC File", double clicked "Report Setup Summary" and got a single line:

altera_reserved_tck 7.788 0.000

There was no line in the table indicating HDMI_TX_CLK

I am using SignalTap where the clock is also the missing clock HDMI_TX_CLK. SignalTap works as expected. The fitter report says it found "2 clocks" consistent with the SDC file. There are some expected warnings from not specifying the periods of input clocks that are specified in PLLs.

One thing that bothers me is this line and is mentioned 5 times in the processing messages:

Info (13166): Register RX_Video:RX_Video_1|RX_Toggle is being clocked by CLK_50_Bank7A

CLK_50_Bank7A is the input clock feeding the PLLs, where a couple are used to create 4 clocks that are muxed onto HDMI_TX_CLK.

In the design Register RX_Video:RX_Video_1|RX_Toggle is being clocked by a clock that selected from1 of 4 clocked the same way HDMI_TX_CLK is created.

So HDMI_TX_CLK is an output clock you are creating and you say it is being used to clock internal logic as well?

Run Report Clocks, not a setup summary, to verify clocks in your design. If it's not showing up in setup summary, that means it's not clocking anything internally.

Many thanks.

The "Report Clocks" does list this clock as I would expect.

HDMI_TX_CLK, or some variant of it, is clocking a lot of logic other pins are dependent on this and are behaving as expected. The same signal is used throughout the design so how can I check that setup and hold times aren't violated?

What are all those false paths you've created? Are you preventing analysis on the paths that are clocked by HDMI_TX_CLK?

Run Report Timing and specify you're looking for paths clocked by this clock.

An extract of the RTL Viewer demonstrates the clock goes to internal logic as well as an I/O pin.

If you put the same clock in both From and To, it will only show paths in that clock domain, which it seems there aren't any. Put it in only one or the other.

Hi,

The clock HDMI_TX_CLK is your output clock right? Have you correctly constraint your input clock?

Take a simple clock divider example, if correctly constraint the input clock, the setup and hold of the output clock can be seen.

Thanks,

Regards,

Sheng

Hi,

I guess you have create clock for your input clock and derive the pll clock.

In the timing analyzer, can you leave the From clock and To clock blank.

Then in Targets section, in either the From or To column search the HDMI_TX_CLK i think may be using get_keepers.

After that report timing.

Thanks,

Regards,

Sheng

Hi,

May I know you able to report the timing?

Thanks,

Regards,

Sheng