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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Clock missing from Timing Analyzer - Report Setup Summary

I have a clock mux along the lines in "ug-qps-03-design-recommendations.pdf" I have set the output clock to be a Global Clock in the Assignment Editor and I give it's minimum period in the sdc file....
Timing
ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


The clock HDMI_TX_CLK is your output clock right? Have you correctly constraint your input clock?

Take a simple clock divider example, if correctly constraint the input clock, the setup and hold of the output clock can be seen.



Thanks,

Regards,

Sheng


Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

I'm sorry, I don't quite follow the philosophy.

The HDMI_TX_CLK is the output from a clock multiplexer that is fed by a couple of PLLs producing a total of 4 clocks, namely standard video clocks, the fastest being 150MHz.

The clock signal feeding the PLLs is a single 25MHz clock.