Occasional Contributor
Super ContributorHi,
The clock HDMI_TX_CLK is your output clock right? Have you correctly constraint your input clock?
Take a simple clock divider example, if correctly constraint the input clock, the setup and hold of the output clock can be seen.
Thanks,
Regards,
Sheng
Occasional ContributorI'm sorry, I don't quite follow the philosophy.
The HDMI_TX_CLK is the output from a clock multiplexer that is fed by a couple of PLLs producing a total of 4 clocks, namely standard video clocks, the fastest being 150MHz.
The clock signal feeding the PLLs is a single 25MHz clock.
Super ContributorDo all the clocks of the PLL (input reference, output clocks) appear in the clocks report (Report Clocks)?
