Hi, I've been analyzing the Altera PCIe Hard-IP cores. I started off with the Qsys PCIe code, since it had the simplest interface. Here's the test setup: * Quartus 11.0, 11.1sp1, 11.1sp2 * Cyclone IV GX Transceiver Starter Kit - x1 PCIe end-point with 125Mhz application clock - x1 PCIe end-point with 62.5MHz application clock * Stratix IV GX Development Kit - x8 PCIe end-point with 250Mhz application clock - x4 PCIe end-point with 125Mhz application clock The Qsys designs are similar to the example provided in the PCIe Compiler Users Guide. I've described the design process and have written automated synthesis scripts (making it easy for anyone to reproduce my results): http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie_analysis.pdf (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_pcie_analysis.pdf) http://www.ovro.caltech.edu/~dwh/correlator/pdf/altera_pcie.zip (http://www.ovro.caltech.edu/%7edwh/correlator/pdf/altera_pcie.zip) The Cyclone IV GX designs were failing timing due to the multi-corner timing optimization setting defaulting to off. The designs pass timing for a -6 speed grade device, but fail for -7 speed grade. This is inconsistent with the PCIe Compiler Users Guide. The Stratix IV GX x8 design still fails timing analysis (ever so slightly). I'm in the process of trying to resolve this via an Altera Service Request. The x4 design has a problem with width negotiation; its sometimes x4, but often x1 or x2, I'm not sure what is wrong. If anyone wants to try these designs, or has any insight or suggestions on where I may have gone wrong, I'd love to know, thanks! Cheers, Dave

Dave, Where is this failing timing? I am currently 'debugging' a design that is.. Quartus 11.0 (I can't run the Qsys system through 11.1, even if I regenerate the Qsys system in 11.1 [which I can do without error]). Custom board Cyclone IV x1 Hard IP PCIe end-point with 125Mhz application clock Simple memory mapped interface to custom logic. This is failing on core-clock -> core clock transfers internal to the hard IP according to Timequest. As far as I can see everything's constrained properly. [Edit] I forgot to say the board's been built with '7 devices, the PCIe spec says the core should work on '8s.[/Edit] I've been meaning to raise a SR for about a week but if you could get it sorted out that would be very helpful. :) Nial

From a quick ckeck of your document I think my design's failing in a similar way. I see you also have a review of Altera's example designs..... I got a design from the Altera wiki "c4gx_qsys_pcie_gen1x1". This is verilog based, my background is VHDL. It took me a long time to realse that at the top level the altgx_reconfig module is connected to the core with undeclared signals (reconfig_fromgxb and reconfig_togxb) which in Verilog are treated as a single bit, so it's effectively not connected . The design works but it's incredibly bad for Altera to be releasing this as an 'example'. I've complained about this elsewhere on this forum so it might be fixed but it's worth keeping an eye out for. Nial

Hi Nial, Thanks for the feedback! I have been very unimpressed with the Altera examples, and the hundreds of disconnected nets that their examples and IP cores generate. It makes it very difficult to spot real errors. All of these warnings could be suppressed with the correct use of generics/parameters and synthesis directives. I did file an SR and I talked to the engineers at Terasic. The guys at Terasic suggested making sure the fitter setting OPTIMIZE_MULTI_CORNER_TIMING was ON. That cleared the errors on the Cyclone IV GX designs, but made no change in the fitter results for the Stratix IV GX designs. I received a response from Altera and it included a couple of example designs. I'll check them out and post an update. Cheers, Dave

Hi all, I've updated the text of the original post above, since I removed the build files (since the design has changed slightly). The design changes were; 1) Turn on multi-corner timing optimization. 2) Turn on the reconfiguration reset input and drive it with a signal derived from the PLL locked output The Cyclone IV GX -6 speed grade devices pass timing now, however, -7 does not for the x1 PCIe with 125MHz application clock (it does with 62.5MHz application clock, at least under 11.0). The Stratix IV GX x8 design does not pass timing either. What a pain ... Cheers, Dave

Thanks for your examples and instructions! This is very useful for understanding of Altera's tools. One more bit of information to consider: we use Altera's dev. board with Stratix IV and used their PCIe+DDR3 example as a starting point. It turns out that when their example is synthesized and P&R'ed, it does not meet timing and the README file says to ignore it! And it actually works on the board! So, the question is if Altera tools say that timing requirements are not met, does it really mean the timing requirements are not met? Conversely, if Altera tools say that timing requirements are met, does it really mean the timing requirements are met? Not a lot of confidence.

Qsys PCIe core fails timing | Altera Community

22 Replies

Altera_Forum
Honored Contributor
14 years ago
Dave,

Where is this failing timing?

I am currently 'debugging' a design that is..
Quartus 11.0 (I can't run the Qsys system through 11.1, even if I regenerate the Qsys system in 11.1 [which I can do without error]).
Custom board
Cyclone IV
x1 Hard IP PCIe end-point with 125Mhz application clock
Simple memory mapped interface to custom logic.

This is failing on core-clock -> core clock transfers internal to the hard IP according to Timequest. As far as I can see everything's constrained properly.

[Edit] I forgot to say the board's been built with '7 devices, the PCIe spec says the core should work on '8s.[/Edit]

I've been meaning to raise a SR for about a week but if you could get it sorted out that would be very helpful.

:)

Nial
Altera_Forum
Honored Contributor
14 years ago
From a quick ckeck of your document I think my design's failing in a similar way.

I see you also have a review of Altera's example designs.....

I got a design from the Altera wiki "c4gx_qsys_pcie_gen1x1".

This is verilog based, my background is VHDL.

It took me a long time to realse that at the top level the altgx_reconfig module is connected to the core with undeclared signals (reconfig_fromgxb and reconfig_togxb) which in Verilog are treated as a single bit, so it's effectively not connected .

The design works but it's incredibly bad for Altera to be releasing this as an 'example'.

I've complained about this elsewhere on this forum so it might be fixed but it's worth keeping an eye out for.

Nial
Altera_Forum
Honored Contributor
14 years ago
Hi Nial,

Thanks for the feedback! I have been very unimpressed with the Altera examples, and the hundreds of disconnected nets that their examples and IP cores generate. It makes it very difficult to spot real errors. All of these warnings could be suppressed with the correct use of generics/parameters and synthesis directives.

I did file an SR and I talked to the engineers at Terasic.

The guys at Terasic suggested making sure the fitter setting OPTIMIZE_MULTI_CORNER_TIMING was ON. That cleared the errors on the Cyclone IV GX designs, but made no change in the fitter results for the Stratix IV GX designs.

I received a response from Altera and it included a couple of example designs. I'll check them out and post an update.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Hi all,

I've updated the text of the original post above, since I removed the build files (since the design has changed slightly). The design changes were;

1) Turn on multi-corner timing optimization.
2) Turn on the reconfiguration reset input and drive it with a signal derived from the PLL locked output

The Cyclone IV GX -6 speed grade devices pass timing now, however, -7 does not for the x1 PCIe with 125MHz application clock (it does with 62.5MHz application clock, at least under 11.0). The Stratix IV GX x8 design does not pass timing either.

What a pain ...

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
Thanks for your examples and instructions! This is very useful for understanding of Altera's tools.

One more bit of information to consider: we use Altera's dev. board with Stratix IV and used their PCIe+DDR3 example as a starting point. It turns out that when their example is synthesized and P&R'ed, it does not meet timing and the README file says to ignore it! And it actually works on the board!

So, the question is if Altera tools say that timing requirements are not met, does it really mean the timing requirements are not met?

Conversely, if Altera tools say that timing requirements are met, does it really mean the timing requirements are met?

Not a lot of confidence.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---

One more bit of information to consider: we use Altera's dev. board with Stratix IV and used their PCIe+DDR3 example as a starting point. It turns out that when their example is synthesized and P&R'ed, it does not meet timing and the README file says to ignore it! And it actually works on the board!

--- Quote End ---
That was part of my initial frustration - none of the example designs appeared to meet timing!

The fact that it works on the board is not too surprising, if you look at the failure paths. Often the failures occur at process extremes, so there's a good chance that you are just 'lucky' and are not operating near that extreme.

The problem is, how can you design a 'robust' system, if the tools complete P&R with timing errors, even after you have told it to perform timing-driven compilation!

--- Quote Start ---

So, the question is if Altera tools say that timing requirements are not met, does it really mean the timing requirements are not met?

--- Quote End ---
It means that your design might fail.

--- Quote Start ---

Conversely, if Altera tools say that timing requirements are met, does it really mean the timing requirements are met?

--- Quote End ---
Yes, timing requirements are all met, under all process variations (assuming the models are conservative).

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
My update on this....

As well as not meeting timing I had a problem with an Error 10232 when I
tried building a Quartus 11.0 Qsys system in Quartus 11.1sp2.

The solution to this was to move a PIO output in the Qsys memory map, this not only cleared the error but from that point on all my designs have been meeting timing.

:confused:

Nial
Altera_Forum
Honored Contributor
14 years ago
Hi Dave,
Did you contact Altera about 'reconfiguration busy' being asserted for ~6ms? Did anyone confirm your timing on another part?
Did you determine if a longer reset period before allowing altgx_reconfig to start improves link negotiation for 4x ?

Was this support entry posted thanks to your design? www altera com/support/kdb/solutions/rd12172009_309.html
Chris
Altera_Forum
Honored Contributor
14 years ago
Hi Chris,

--- Quote Start ---

Did you contact Altera about 'reconfiguration busy' being asserted for ~6ms? Did anyone confirm your timing on another part?

--- Quote End ---

I didn't contact Altera about this aspect (my discussions with them were regarding the failure to meet timing). I don't recall if I tested this on multiple parts.

--- Quote Start ---

Did you determine if a longer reset period before allowing altgx_reconfig to start improves link negotiation for 4x ?

--- Quote End ---

I didn't try. Have you?

--- Quote Start ---

Was this support entry posted thanks to your design? www altera com/support/kdb/solutions/rd12172009_309.html

--- Quote End ---

I don't think so. I do recall seeing recommendations like this, though many of the example designs neglect to implement it.

Cheers,
Dave
Altera_Forum
Honored Contributor
14 years ago
So far I haven't had a problem negotiating at x4 gen2. My design is a custom PCB with different clock sources to the dev board. The reconfig_pll is driven by an external free running clock at 125Mhz on LVDS pins. Also the design passes timing - perhaps this was cleaned up in QuartusII v12. I'm not in a position to measure the reconfiguration time as no chipscope support for my cable.

Chris

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Qsys PCIe core fails timing

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