Qsys PCIe core fails timing

Hi all,

I've updated the text of the original post above, since I removed the build files (since the design has changed slightly). The design changes were;

1) Turn on multi-corner timing optimization.

2) Turn on the reconfiguration reset input and drive it with a signal derived from the PLL locked output

The Cyclone IV GX -6 speed grade devices pass timing now, however, -7 does not for the x1 PCIe with 125MHz application clock (it does with 62.5MHz application clock, at least under 11.0). The Stratix IV GX x8 design does not pass timing either.

What a pain ...

Cheers,

Dave