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TimHagen's avatar
TimHagen
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5 years ago

MAX10 TSE reference design

This is the MAX10 reference design - this was modified from what is posted on the design store that does not run:

The TEST_MAC_LB 1000M and TEST_MAC_PHY_LB 1000M tests run successfully. 1G and 10/100 were tested.

The source files were moved around so they are not in generated directories which is not a good idea. The PLL and SDC timing was corrected. The design passes timing now.

The PHY setup was also corrected. The original had the PLL phase shifted the TX clock and the TCL scripts told the PHY to phase shift. So the data was changing at the same time it was being captured.

The TCL scripts were missing in the V18 download. They were pulled from the original Quartus version 15 download and added to the zip. The attachment is a zip of the design dir.

The TCL scripts have a while loop that looks for status that isn’t necessary. So there is a long delay that seems to be needless but I didn’t change it just in case there is a reason for it.

This work was done by Scott Prigmore of the embedded cluster.

14 Replies

  • Johny123's avatar
    Johny123
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    Hey Tim, thanks for the update here. Is there also a working reference designs for the max10 webserver (remote update) with tse-mac available in the store. The existing reference designs do not pass the qsys build from 17.0 onwards.

    • drbarryh's avatar
      drbarryh
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      Hi Johny,

      Yes that;s what i discovered too. The 2017 one was upgradeable to Quartus 2018, then it builds and appears to pass timing, but al the TCL commands failed....such as  TEST_MAC_PHY_LB 1000M, TEST_MAC_LB 1000M. I need to use the TSE in Gigabit mode. It seems like Tim says the failures are due to bad timing.

      cheers, Dr Barry H

       

  • Hello Dr Barry,

    Good day to you. Here's some insights from us regarding your earlier queries regarding Iperf3.  Hope this can be helpful.

    I'm looking into your latest question meanwhile.

    • drbarryh's avatar
      drbarryh
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      Hi Pavee, Thanks for the Forum_TSE word document. I think i was forced somehow into using IPERF3 and not IPERF by LINUX on the Raspberry PI5 i was using . Sorry i din't know that iperf and iperf3 are incompatible...but that's quite typical of applications !

      I assume your iperf examples are done on a windows machine ? Maybe windows 10 ?
      I will retry the iperf tests using my windows 10 machine and only use iperf.

      Yes please do look into my other questions regards how to modify your quartus TSE designs by removing DMA and OS, and usinga NIOSV/m instead of a NIOSV/G and using Avalon FIFOs to interface to the TSE from out SV application logic. Thanks for the help, Dr Barry H

  • Hi Tim,

    Many thanks for the MAX10 TSE reference design. It had gotten into quite a mess i think ! Its great that it was tested at 1G which is what i need to use. All my tests had been failing but as you say: not a good idea to change data and clock simultaneously! I will try your zipped project and see if i can get it to compiled and working properly. Which Quartus Version does this project belong to please ? I am hoping to use it in a Quartus 25.1 Std project eventually.

    Thanks are also due then to Scott Prigmore for doing the fix up work !

    Thanks very much, Dr Barry H

  • Hi again Tim,

    I noticed after unzipping your attached zip file that the design was done in Quartus 2018.1. I have Quartus 2018.0 ....will it make a difference using that earlier version ? I was thinking that usually small increments to Quartus don't matter much, but maybe i will download Quartus 2018.1 to be sure.

    Now when i compiled your project it does compile but i get some timing failures like the ones you can see in my attached screenshot on the Tx side. I wonder if i need to apply any compiler or fitter specific options to get the best performance and eliminate these timing failures ? There are a lot of options in the advanced compiler and fitter options list in Quartus compiler section !

    Now to the results. I downloaded my bit file to my MAX10 Dev board and when i try either the TEST_MAC_LB "1000M"  or TEST_MAC_LB "100M" or TEST_MAC_LB "10M"  after running the main.tcl sctipt from the sc_tcl directory i only ever see 10000 Tx frames sent but 0 frames received when i review the stats_chk results in system console.

    I have am using an ALTERA MAX10 10M50-C Development board, which is connected to a windows 10 PC and it seems to be connecting OK because i can see the Yellow lights are lit on the MAX10 dev board ETHER A RJ45 port.

    Can you suggest what steps i am missing or what i am doing wrong please ? I know you all of your Loopback tests passed at 10/100/1000 speeds so i am not sure why mine all seem to be failing (again!).

    In fact can you possibly add a screenshot which shows the results you get when you run these Loopback tests please if that's possible ? It would be very helpful and encouraging to actually see this TSE working !!

    Thanks for your help, Dr Barry H

     

  • Hello Barry,

     

    Looking at thread history, its 5 years ago thread. Hence I'll go ahead and close this Forum but you may continue to work on this thread for community support. If you need further help, please file a new Forum.

     

    Regards,

    Pavee

    • drbarryh's avatar
      drbarryh
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      Hello Pavee,Thansk for your message ...BUT....

      Yes it may be 5 years old this thread BUT the same problems still exist obviously which is why i am asking the same question ? ALTERA sill has the failing Example design par files ,...namely all of them fail for different reasons. ALTERA i think should fix these problems once and for all don't you think and put up a TSE MAX10 example design the is a) up to date b) has better documentation c) actually works in Quartus and Platform Designer ?

      Best regards, Dr Barry H

      • paveetirrasrie_Altera's avatar
        paveetirrasrie_Altera
        Icon for Frequent Contributor rankFrequent Contributor

        Hello Barry,

         

        Apologies for the inconvenience caused while working with our Reference design.  

        Definitely agreeing with you on this matter. I will bring this matter to my internal team and will keep you posted with this.

         

        Regards,

        Pavee