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ContributorHello Pavee,Thansk for your message ...BUT....
Yes it may be 5 years old this thread BUT the same problems still exist obviously which is why i am asking the same question ? ALTERA sill has the failing Example design par files ,...namely all of them fail for different reasons. ALTERA i think should fix these problems once and for all don't you think and put up a TSE MAX10 example design the is a) up to date b) has better documentation c) actually works in Quartus and Platform Designer ?
Best regards, Dr Barry H
Frequent ContributorHello Barry,
Apologies for the inconvenience caused while working with our Reference design.
Definitely agreeing with you on this matter. I will bring this matter to my internal team and will keep you posted with this.
Regards,
Pavee
ContributorGreetings Pavee and thanks for your support in this matter !
To add to this CASE here is another fact: We already do know that the TSE is able to work on a MAX10 development kit because. Looking at the "MAX® 10 FPGA Development Kit User Guide" on page 12 "2.4.1 it says. Step 1: Connect to the Board Update Portal" this Board Update Portal uses a TSE MAC to connect to ALTERAS Board Update Portal which then allows users to update images in the USER FLASH areas of the dev kit, using their own ELF files and a FPGA bit file.
I have tried this and i can report that it does work, and my MAX 10 Dev Kit gets an IP address from my Router over DHCP, and i can connect to the BUP using that IP address, which means the TSE + MSC + PHY are working in full 1G Duplex mode at 1G. So the TSE is definitely able to connect and run the ALTERA BUP server. I don't have access to that project though because its embedded in the FLASH of the MAX10 Dev Kit so i can't see how it is implemented to try to copy it.
I have added two screenshots to this CASE which shows the startup phase and then the connection phase to the ALTERA BUP, using my MAX10 Dev Kit ad the TSE + MARVELL PHY. This was achieved using the Board Update Portals design located in my Dev Kits FLASH memory, and it was done only recently.
Thanks, Dr Barry H
Frequent ContributorThanks Barry for the details.
The FLASH in Max10 is meant to be encrypted, It's not accessible to public.
To update, we currently has TSE IP + NiosV design in 23.1std, work in progress. May I know what is your requirement with our design, do you prefer to have it with DHCP enabled or Static IP would work for you?
Regards,
Pavee
ContributorHi Paveet, thanks for the update, and that should be OK. We are using 25.1 std but can do an upgrade if possible from 23.1 i guess.
In our final system design we will probably be using a direct Ethernet connection, with static IP Address, so without any DHCP server. But with DHCP is OK too as long as we can get it working as the main priority !
Can you tell me your system design ? Is it using any DMA (SGDMA?) ? And is it for MAX10 FPGA ? Also how do you test it in real FPGA ....using a Windows or Linux PC to connect to ?
Thanks for your help Pavvet,
Dr Barry H
