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Frequent ContributorHello Dr Barry,
Good day to you. Here's some insights from us regarding your earlier queries regarding Iperf3. Hope this can be helpful.
I'm looking into your latest question meanwhile.
ContributorHi Pavee, Thanks for the Forum_TSE word document. I think i was forced somehow into using IPERF3 and not IPERF by LINUX on the Raspberry PI5 i was using . Sorry i din't know that iperf and iperf3 are incompatible...but that's quite typical of applications !
I assume your iperf examples are done on a windows machine ? Maybe windows 10 ?
I will retry the iperf tests using my windows 10 machine and only use iperf.
Yes please do look into my other questions regards how to modify your quartus TSE designs by removing DMA and OS, and usinga NIOSV/m instead of a NIOSV/G and using Avalon FIFOs to interface to the TSE from out SV application logic. Thanks for the help, Dr Barry H
Frequent ContributorHello Dr Barry,
Kindly let me know if you need further support on this matter.
Regards,
Pavee
ContributorHi Pavee,
Thanks for asking, and yes i still need your support to get the TSE working in a Bare Metal Design on a MAX10 Developemnt board. I have been trying to do this mysefl without achieving success (e.g. i cannot see any UDP or TCP packets on a PI5 i connect my MAX10 dev board to. I can send you my complete FPGA project along with muy C software i am using to try to test out this system. Possibly with your expects eye you might be able to spot bugs and what i am doing wrong ? That would be a great help to get the TSE working on baremetaul.
We actually only need UDP communications to work at 1G. My current design targets the TSE in its simpletes mode, which is using a small MAC at 1G. This is all we need working for this project. It looks to me like the MARVELL 88E1111 PHY is correctly auto negottatinmg to the PI5, but then the TSE tries to send UDP packets to the PI5 and using WIRESHARK (at the Pi5 end) i dont; see any UDP Traffic.
If you can provide an email address i can send you my project in 7zip format ?
Thanks for your help,
Dr Barry H
Frequent ContributorHello Dr Barry,
Apologies for the delayed response.
The design that we have shared uses MSGDMA and relevant drivers for data transfer between memory and TSE.
MSGDMA is fast and can operate without disturbing the CPU.
To answer the questions, Yes, the design can be modified to use Avalon FIFOs. But that would require CPU intervention to transfer the data from FIFO to the memory and vice versa.
This "may" bring down the throughput as the CPU would be busy frequently. We do not have exact data on how it would impact.
If you're okay with that, you can use the Avalon FIFO IPs. But you will have to develop the complete baremetal application.
I suggest to look into the TSE IP example design where they are using a custom logic to generate packets and loop it back via TSE.
It is a baremetal application and uses JTAG to Avalon® memory-mapped interface Address Decoder for data transfers.
Here is the link to the IP example design doc- https://docs.altera.com/r/docs/813899/25.3.1/triple-speed-ethernet-ip-design-example-user-guide-agilextm-3-and-agilextm-5-fpgas-and-socs/100/1000-ethernet-mac-design-example-with-1000base-x/sgmii-2xtbi-pcs-with-gts-transceiver
Regarding the Nios V/m porting, we have a design with Nios V/m + TSE on Agilex 7 SiSoc devkit showcasing iperf and SSS applications based on ucOSII.
You may refer to that design in the links below:
Again, this is with ucOSII and not a baremetal application.
You will have to refer to the TSE IP example design to write the baremetal code for TSE init and operation.
Regards,
Pavee
