Forum Discussion

TimHagen's avatar
TimHagen
Icon for New Contributor rankNew Contributor
6 years ago

MAX10 TSE reference design

This is the MAX10 reference design - this was modified from what is posted on the design store that does not run: The TEST_MAC_LB 1000M and TEST_MAC_PHY_LB 1000M tests run successfully. 1G and 10/...
paveetirrasrie_Altera's avatar
paveetirrasrie_Altera
Icon for Frequent Contributor rankFrequent Contributor
5 months ago

Hello Barry,

 

Looking at thread history, its 5 years ago thread. Hence I'll go ahead and close this Forum but you may continue to work on this thread for community support. If you need further help, please file a new Forum.

 

Regards,

Pavee

drbarryh's avatar
drbarryh
Icon for Contributor rankContributor
5 months ago

Hello Pavee,Thansk for your message ...BUT....

Yes it may be 5 years old this thread BUT the same problems still exist obviously which is why i am asking the same question ? ALTERA sill has the failing Example design par files ,...namely all of them fail for different reasons. ALTERA i think should fix these problems once and for all don't you think and put up a TSE MAX10 example design the is a) up to date b) has better documentation c) actually works in Quartus and Platform Designer ?

Best regards, Dr Barry H

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    5 months ago

    Hello Barry,

     

    Apologies for the inconvenience caused while working with our Reference design.  

    Definitely agreeing with you on this matter. I will bring this matter to my internal team and will keep you posted with this.

     

    Regards,

    Pavee

    • drbarryh's avatar
      drbarryh
      Icon for Contributor rankContributor
      5 months ago

      Greetings Pavee and thanks for your support in this matter !


      To add to this CASE here is another fact: We already do know that the TSE is able to work on a MAX10 development kit because. Looking at the "MAX® 10 FPGA Development Kit User Guide" on page 12 "2.4.1 it says. Step 1: Connect to the Board Update Portal" this Board Update Portal  uses a TSE MAC to connect to ALTERAS Board Update Portal which then allows users to update images in the USER FLASH areas of the dev kit, using their own ELF files and a FPGA bit file.

      I have tried this and i can report that it does work, and my MAX 10 Dev Kit gets an IP address from my Router over DHCP, and i can connect to the BUP using that IP address, which means the TSE + MSC + PHY are working in full 1G Duplex mode at 1G. So the TSE is definitely able to connect and run the ALTERA BUP server. I don't have access to that project though because its embedded in the FLASH of the MAX10 Dev Kit so i can't see how it is implemented to try to copy it.

      I have added two screenshots to this CASE which shows the startup phase and then the connection phase to the ALTERA BUP, using my MAX10 Dev Kit ad the TSE + MARVELL PHY. This was achieved using the Board Update Portals design located in my Dev Kits FLASH memory, and it was done only recently.

      Thanks, Dr Barry H

      • paveetirrasrie_Altera's avatar
        paveetirrasrie_Altera
        Icon for Frequent Contributor rankFrequent Contributor
        5 months ago

        Thanks Barry for the details. 

        The FLASH in Max10 is meant to be encrypted, It's not accessible to public. 

         

        To update, we currently has TSE IP + NiosV design in 23.1std, work in progress. May I know what is your requirement with our design, do you prefer to have it with DHCP enabled or Static IP would work for you?

         

        Regards,

        Pavee