Qsys PCIe core fails timing

Hi Nial,

Thanks for the feedback! I have been very unimpressed with the Altera examples, and the hundreds of disconnected nets that their examples and IP cores generate. It makes it very difficult to spot real errors. All of these warnings could be suppressed with the correct use of generics/parameters and synthesis directives.

I did file an SR and I talked to the engineers at Terasic.

The guys at Terasic suggested making sure the fitter setting OPTIMIZE_MULTI_CORNER_TIMING was ON. That cleared the errors on the Cyclone IV GX designs, but made no change in the fitter results for the Stratix IV GX designs.

I received a response from Altera and it included a couple of example designs. I'll check them out and post an update.

Cheers,

Dave