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pradeep_12's avatar
pradeep_12
Icon for New Contributor rankNew Contributor
1 month ago

R-TILE PIPE DIRECT MODE SIMULATION PHY STATUS ISSUE IN RESET RELEASE SEQUENCE

HI,

     I am currently working on r-tile pipe direct mode simulation in questasim.  So, initially i have generated r-tile ip with configuration of pipe direct mode, 16x1. I have generated hdls using generate hdl option(enabling verilog,questasim). I have written pipe control fsm to provide control inputs to r-tile ip.

     Ref_clock1,ref_clock2 frequency is 100mhz. Reconfig_clock frequency is 100mhz.  pipe_direct_pld_tx_clk_out_o from ip is 500mhz(validated in sim)

     So, i start with providing ninit_done using reset release ip. once nint_done goes low, i am providing pin_perst_n to high. then pin_perst_n_o goes high. After sometime, pipe_direct_pld_tx_clk_out_o becomes active.  So, i am waiting for ln0_pipe_direct_tx_transfer_en_o to goes high. once this signal goes high, i will release ln0_pipe_direct_pld_pcs_rst_n_i to high. I am checking the phy signal to toggle. but from beginning itself it stays low, it never toggles.

Along with this standard procedure, i tried 2 more possibilities

  1. i tried,  After i released the  ln0_pipe_direct_pld_pcs_rst_n_i to high. I provided the ln0_pipe_direct_txdetectrx_i to high. No response from phy_status.
  2. After i released the  ln0_pipe_direct_pld_pcs_rst_n_i to high. I provided the ln0_pipe_direct_txdetectrx_i , rx_standby to high. still No response from phy_status

I am attaching some screenshots of waveforms. Kinly look into it and help me out. I am really stuck at midway..

 

 

 

Pcie
Transceiver

2 Replies

  • ai_responder's avatar
    ai_responder
    Icon for Community Manager rankCommunity Manager
    1 month ago

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  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi pradeep_12 ,

    The guide shows txdetectrx_i being asserted while the lane is in P1 and the transmitter is electrically idle; it must not simply be held at an arbitrary level after PCS reset. Your waveform appears to leave the lane in P1 and does not show the complete detect-command/deassertion sequence.

     

    Main issues visible in your waveform

    • powerdown_i appears to remain at 2'b10/P1. You must transition it to P0 after receiver detection.
    • txelecidle_i is not shown. Drive it to 4'hF during P1 receiver detection.
    • Do not assert rxstandby_i during bring-up; that requests RX standby and prevents normal receiver activity. The PHY reports standby through rxstandbystatus_o.
    • txdetectrx_i should be treated as a receiver-detect command and then returned inactive after the phystatus/rxstatus response.
    • Use a sticky debug latch for phystatus, because a one-cycle pulse can easily be missed in a wide Questasim waveform view
    • After the receiver-detect pulse, you will only see cdrlockstatus_o, cdrlock2data_o, RX clock, and reset_status_n_o become active if the simulation includes a valid serial link partner or loopback data. 

    Regards,
    Wincent_Altera