R-TILE PIPE DIRECT MODE SIMULATION PHY STATUS ISSUE IN RESET RELEASE SEQUENCE

HI,

     I am currently working on r-tile pipe direct mode simulation in questasim.  So, initially i have generated r-tile ip with configuration of pipe direct mode, 16x1. I have generated hdls using generate hdl option(enabling verilog,questasim). I have written pipe control fsm to provide control inputs to r-tile ip.

     Ref_clock1,ref_clock2 frequency is 100mhz. Reconfig_clock frequency is 100mhz.  pipe_direct_pld_tx_clk_out_o from ip is 500mhz(validated in sim)

     So, i start with providing ninit_done using reset release ip. once nint_done goes low, i am providing pin_perst_n to high. then pin_perst_n_o goes high. After sometime, pipe_direct_pld_tx_clk_out_o becomes active.  So, i am waiting for ln0_pipe_direct_tx_transfer_en_o to goes high. once this signal goes high, i will release ln0_pipe_direct_pld_pcs_rst_n_i to high. I am checking the phy signal to toggle. but from beginning itself it stays low, it never toggles.

Along with this standard procedure, i tried 2 more possibilities

1. i tried,  After i released the  ln0_pipe_direct_pld_pcs_rst_n_i to high. I provided the ln0_pipe_direct_txdetectrx_i to high. No response from phy_status.
2. After i released the  ln0_pipe_direct_pld_pcs_rst_n_i to high. I provided the ln0_pipe_direct_txdetectrx_i , rx_standby to high. still No response from phy_status

I am attaching some screenshots of waveforms. Kinly look into it and help me out. I am really stuck at midway..