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Altera_Forum
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14 years ago

Qsys PCIe core fails timing

Hi, I've been analyzing the Altera PCIe Hard-IP cores. I started off with the Qsys PCIe code, since it had the simplest interface. Here's the test setup: * Quartus 11.0, 11.1sp1, 11.1...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Dave,

Where is this failing timing?

I am currently 'debugging' a design that is..

Quartus 11.0 (I can't run the Qsys system through 11.1, even if I regenerate the Qsys system in 11.1 [which I can do without error]).

Custom board

Cyclone IV

x1 Hard IP PCIe end-point with 125Mhz application clock

Simple memory mapped interface to custom logic.

This is failing on core-clock -> core clock transfers internal to the hard IP according to Timequest. As far as I can see everything's constrained properly.

[Edit] I forgot to say the board's been built with '7 devices, the PCIe spec says the core should work on '8s.[/Edit]

I've been meaning to raise a SR for about a week but if you could get it sorted out that would be very helpful.

:)

Nial