Qsys PCIe core fails timing

Thanks for your examples and instructions! This is very useful for understanding of Altera's tools.

One more bit of information to consider: we use Altera's dev. board with Stratix IV and used their PCIe+DDR3 example as a starting point. It turns out that when their example is synthesized and P&R'ed, it does not meet timing and the README file says to ignore it! And it actually works on the board!

So, the question is if Altera tools say that timing requirements are not met, does it really mean the timing requirements are not met?

Conversely, if Altera tools say that timing requirements are met, does it really mean the timing requirements are met?

Not a lot of confidence.