Qsys PCIe core fails timing

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One more bit of information to consider: we use Altera's dev. board with Stratix IV and used their PCIe+DDR3 example as a starting point. It turns out that when their example is synthesized and P&R'ed, it does not meet timing and the README file says to ignore it! And it actually works on the board!

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That was part of my initial frustration - none of the example designs appeared to meet timing!

The fact that it works on the board is not too surprising, if you look at the failure paths. Often the failures occur at process extremes, so there's a good chance that you are just 'lucky' and are not operating near that extreme.

The problem is, how can you design a 'robust' system, if the tools complete P&R with timing errors, even after you have told it to perform timing-driven compilation!

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So, the question is if Altera tools say that timing requirements are not met, does it really mean the timing requirements are not met?

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It means that your design might fail.

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Conversely, if Altera tools say that timing requirements are met, does it really mean the timing requirements are met?

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Yes, timing requirements are all met, under all process variations (assuming the models are conservative).

Cheers,

Dave