Qsys PCIe core fails timing

From a quick ckeck of your document I think my design's failing in a similar way.

I see you also have a review of Altera's example designs.....

I got a design from the Altera wiki "c4gx_qsys_pcie_gen1x1".

This is verilog based, my background is VHDL.

It took me a long time to realse that at the top level the altgx_reconfig module is connected to the core with undeclared signals (reconfig_fromgxb and reconfig_togxb) which in Verilog are treated as a single bit, so it's effectively not connected .

The design works but it's incredibly bad for Altera to be releasing this as an 'example'.

I've complained about this elsewhere on this forum so it might be fixed but it's worth keeping an eye out for.

Nial