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Altera_Forum
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14 years ago

Qsys PCIe core fails timing

Hi, I've been analyzing the Altera PCIe Hard-IP cores. I started off with the Qsys PCIe code, since it had the simplest interface. Here's the test setup: * Quartus 11.0, 11.1sp1, 11.1...
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Altera_Forum
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13 years ago

Hi Chris,

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Did you contact Altera about 'reconfiguration busy' being asserted for ~6ms? Did anyone confirm your timing on another part?

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I didn't contact Altera about this aspect (my discussions with them were regarding the failure to meet timing). I don't recall if I tested this on multiple parts.

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Did you determine if a longer reset period before allowing altgx_reconfig to start improves link negotiation for 4x ?

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I didn't try. Have you?

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Was this support entry posted thanks to your design? www altera com/support/kdb/solutions/rd12172009_309.html

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I don't think so. I do recall seeing recommendations like this, though many of the example designs neglect to implement it.

Cheers,

Dave