Hi @JohnT_Intel FPGA_dclk output of the PFL (Parallel Flash Loader). FPGA_dclk is an output of the PFL and gets propagated to my top level wrapper output port. The FPGA_dclk is used normally to configure the FPGA. How to constrain FPGA_dclk? With an output delay corresponding to the input clock? I used create_clock command at the input pin (in_clk), the tool should automatically generate the correct FPGA_dclk on the output. The kit I received for max5 from you specified the following DCLK constraint : set_output_delay -add_delay -max -clock [get_clocks {clkin_50}] 0.000 [get_ports {fpga_dclk}]set_output_delay -add_delay -min -clock [get_clocks {clkin_50}] 0.000 [get_ports {fpga_dclk}] It specified 0.000 output delay. Is this right? No delay at all on the output DCLK? I had a warning "Min rise delay is equal to max rise delay", if use 0.000 So I used : create_clock -name {clk} -period 100.000 -waveform { 0.000 50.000 } [get_ports {in_clk}] # Create the associated virtual input clockcreate_clock -name {clk_virt} -period 100.000 -waveform { 0.000 50.000 } set_output_delay -clock clk_virt \-max 0.001 \[get_ports fpga_dclk] set_output_delay -clock clk_virt \-min 0.000 \[get_ports fpga_dclk] But is this right ? Back to my original question. How do I properly constrain DCLK which is currently an output ? Using set_output_delay ? If yes, please comment on the above in bold. What -max (for setup) / -min (for hold) values can I use? Regards, Kevin

Hi @JohnT_Intel That kit constraints file looks wrong wrt the DCLK constraint. Please comment here. Wrt the PFL FPGA IP User Guide document this needs to be constrained as a generated clock. I did this. Reviewing the rest of my wrapper wrt PFL timing constraints. It lists many false paths and set_max_delay ones for input/output asynchronous signals in the PFL IP user Guide. If any issues will get back. Regards, Kevin

Need to use set_max_delay constraints for the following wrt PFL IP User guide : flash_nce flash_addr flash_data fpga_data Cannot figure out best set_max_delay values ? to use . Any help on this will be appreciated. ---- # Output delay (flash_addr, flash_nce) = Distributed timing budget - board delay = Timing budget (major) - board delay from PFL to flash # Taccess (flash ROM time specification during normal access) = 100ns ? (Table 42 of flash spec tacc ?)# Timing budget = [roundup(Taccess_pfl/Tpfl_clk) + 1]*Tpfl_clk - Taccess = [roundup(100ns/100ns + 1]*100ns - Taccess = 200ns - Taccess = 200ns - 100ns? = 100ns? set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_nce] ?set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_addr[*]] ? # Read mode (PFL to Flash ROM)# Input delay (flash_data) = Timing budget (minor) - board delay from flash to PFLset_max_delay -from [get_ports flash_data[*]] -to [get_ports {in_clk}] ? # Delay value determined by the board delay and Tsu/Tdh of the FPGA ? set_output_delay -clock clk_virt -max ? [get_ports fpga_data[*]] set_output_delay -clock clk_virt -min ? [get_ports fpga_data[*]]

Hi @JohnT_Intel I am getting confused now ! 2 different PFL User Guides with 2 different constraint suggestions! Which one is right ?? https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf flash_nce set_false_path flash_addr set_false_path flash_data Normal read mode:set_false_path• Burst read mode:set_input_delay fpga_data set_output_delay fpga_dclk set_output_delay ----- https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html 1.4.2.1. Constraining Clock Signal 1.4.2.2. Constraining Synchronous input and Output ports 1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports 1.4.2.4. Summary of PFL Timing constraints flash_nce set_max_delay -from pfl_clk -to <port> flash_addr set_max_delay -from pfl_clk -to <port> flash_data Read mode (PFL to Flash ROM) set_max_delay -from <port> to pfl_clk Write mode (Flash ROM to PFL) set_false_path fpga_data set_output_delay -clock fpga_dclk <port> fpga_dclk Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>

Hi,Normally, the FPGA_dclk signal is not constrain on the delay. The available constrain is input clk to dclk ratio.Please refer to Table 8 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf

Hi @JohnT_Intel That link you sent me lists set_output_delay on the fpga_dclk ! I noticed another doc that lists the fpga_dclk as a generated clk which I constrained. I sent another message with the differences between the 2 docs which was confusing. Did you see this ? This lists other PFL constraints too. It states false paths in one of them whereas set_max_delays in the other one. This is confusing. Which one is right?

How to properly constrain the PFL for STA

22 Replies

Knug
Contributor
5 years ago
Hi @JohnT_Intel

That kit constraints file looks wrong wrt the DCLK constraint. Please comment here.

Wrt the PFL FPGA IP User Guide document this needs to be constrained as a generated clock. I did this.

Reviewing the rest of my wrapper wrt PFL timing constraints.

It lists many false paths and set_max_delay ones for input/output asynchronous signals in the PFL IP user Guide.

If any issues will get back.

Regards,

Kevin
- Knug
  Contributor
  5 years ago
  Need to use set_max_delay constraints for the following wrt PFL IP User guide :
  
  flash_nce
  
  flash_addr
  
  flash_data
  
  fpga_data
  
  Cannot figure out best set_max_delay values ? to use . Any help on this will be appreciated.
  
  ----
  
  # Output delay (flash_addr, flash_nce) = Distributed timing budget - board delay = Timing budget (major) - board delay from PFL to flash
  
  # Taccess (flash ROM time specification during normal access) = 100ns ? (Table 42 of flash spec tacc ?)
  # Timing budget = [roundup(Taccess_pfl/Tpfl_clk) + 1]*Tpfl_clk - Taccess = [roundup(100ns/100ns + 1]*100ns - Taccess = 200ns - Taccess = 200ns - 100ns? = 100ns?
  
  set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_nce] ?
  set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_addr[*]] ?
  
  # Read mode (PFL to Flash ROM)
  # Input delay (flash_data) = Timing budget (minor) - board delay from flash to PFL
  set_max_delay -from [get_ports flash_data[*]] -to [get_ports {in_clk}] ?
  
  # Delay value determined by the board delay and Tsu/Tdh of the FPGA ?
  
  set_output_delay -clock clk_virt -max ? [get_ports fpga_data[*]]
  
  set_output_delay -clock clk_virt -min ? [get_ports fpga_data[*]]
  - Knug
    Contributor
    5 years ago
    Hi @JohnT_Intel
    
    I am getting confused now !
    
    2 different PFL User Guides with 2 different constraint suggestions! Which one is right ??
    
    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
    
    flash_nce set_false_path
    
    flash_addr set_false_path
    
    flash_data Normal read mode:
    set_false_path
    • Burst read mode:
    set_input_delay
    
    fpga_data set_output_delay
    
    fpga_dclk set_output_delay
    
    -----
    
    https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html
    
    1.4.2.1. Constraining Clock Signal
    
    1.4.2.2. Constraining Synchronous input and Output ports
    
    1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports
    
    1.4.2.4. Summary of PFL Timing constraints
    
    flash_nce set_max_delay -from pfl_clk -to <port>
    
    flash_addr set_max_delay -from pfl_clk -to <port>
    
    flash_data
    
    Read mode (PFL to Flash ROM)
    set_max_delay -from <port> to pfl_clk
    
    Write mode (Flash ROM to PFL) set_false_path
    
    fpga_data set_output_delay -clock fpga_dclk <port>
    
    fpga_dclk
    
    Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>
JohnT_Altera
Regular Contributor
5 years ago
Hi,

Normally, the FPGA_dclk signal is not constrain on the delay. The available constrain is input clk to dclk ratio.

Please refer to Table 8 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
- Knug
  Contributor
  5 years ago
  Hi @JohnT_Intel
  
  That link you sent me lists set_output_delay on the fpga_dclk !
  
  I noticed another doc that lists the fpga_dclk as a generated clk which I constrained.
  
  I sent another message with the differences between the 2 docs which was confusing. Did you see this ?
  
  This lists other PFL constraints too. It states false paths in one of them whereas set_max_delays in the other one. This is confusing. Which one is right?
  - Knug
    Contributor
    5 years ago
    Hi @JohnT_Intel
    
    This is what I was talking about :
    
    2 different PFL User Guides with 2 different constraint suggestions! Which one is right ??
    
    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
    
    flash_nce
    
    set_false_path
    
    flash_addr
    
    set_false_path
    
    flash_data
    
    Normal read mode:
    set_false_path
    • Burst read mode:
    set_input_delay
    
    fpga_data
    
    set_output_delay
    
    fpga_dclk
    
    set_output_delay
    
    -----
    
    https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html
    
    1.4.2.1. Constraining Clock Signal
    
    1.4.2.2. Constraining Synchronous input and Output ports
    
    1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports
    
    1.4.2.4. Summary of PFL Timing constraints
    
    flash_nce
    
    set_max_delay -from pfl_clk -to <port>
    
    flash_addr
    
    set_max_delay -from pfl_clk -to <port>
    
    flash_data
    
    Read mode (PFL to Flash ROM)
    
    set_max_delay -from <port> to pfl_clk
    
    Write mode (Flash ROM to PFL) set_false_path
    
    fpga_data
    
    set_output_delay -clock fpga_dclk <port>
    
    fpga_dclk
    
    Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>
JohnT_Altera
Regular Contributor
5 years ago
Hi,

Could you send to me through private message?
- Knug
  Contributor
  5 years ago
  Hi @JohnT_Intel
  
  I generated another ticket with that and it was deleted again. It is important to get the constraints right. What is going on here ?
  
  why there are differences in constraints between the 2 intel docs ??
  
  How do I send a private message? & why my latest messages get deleted ?
  
  What is your private email address ?
  
  Not happy with this matter .
  - Knug
    Contributor
    5 years ago
    Hi @JohnT_Intel
    
    I just sent it as a private message. Did you receive it?
JohnT_Altera
Regular Contributor
5 years ago
Hi,

I have received and have reply to you.
- Knug
  Contributor
  5 years ago
  Hi @JohnT_Intel
  
  My last 3 Messages to the private email got back :
  
  Delivery has failed to these recipients or groups:
  
  [email protected] ([email protected]) <mailto:[email protected]>
  
  Your message couldn't be delivered. Despite repeated attempts to deliver your message, querying the Domain Name System (DNS) for the recipient's domain location information failed.
JohnT_Altera
Regular Contributor
5 years ago
Hi,

I send another email to you so that you can reply to it.

Forum Discussion

How to properly constrain the PFL for STA

22 Replies

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