Contributor
ContributorHi @JohnT_Intel
That kit constraints file looks wrong wrt the DCLK constraint. Please comment here.
Wrt the PFL FPGA IP User Guide document this needs to be constrained as a generated clock. I did this.
Reviewing the rest of my wrapper wrt PFL timing constraints.
It lists many false paths and set_max_delay ones for input/output asynchronous signals in the PFL IP user Guide.
If any issues will get back.
Regards,
Kevin
ContributorNeed to use set_max_delay constraints for the following wrt PFL IP User guide :
Cannot figure out best set_max_delay values ? to use . Any help on this will be appreciated.
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# Output delay (flash_addr, flash_nce) = Distributed timing budget - board delay = Timing budget (major) - board delay from PFL to flash
# Taccess (flash ROM time specification during normal access) = 100ns ? (Table 42 of flash spec tacc ?)
# Timing budget = [roundup(Taccess_pfl/Tpfl_clk) + 1]*Tpfl_clk - Taccess = [roundup(100ns/100ns + 1]*100ns - Taccess = 200ns - Taccess = 200ns - 100ns? = 100ns?
set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_nce] ?
set_max_delay -from [get_ports {in_clk}] -to [get_ports flash_addr[*]] ?
# Read mode (PFL to Flash ROM)
# Input delay (flash_data) = Timing budget (minor) - board delay from flash to PFL
set_max_delay -from [get_ports flash_data[*]] -to [get_ports {in_clk}] ?
# Delay value determined by the board delay and Tsu/Tdh of the FPGA ?
set_output_delay -clock clk_virt -max ? [get_ports fpga_data[*]]
set_output_delay -clock clk_virt -min ? [get_ports fpga_data[*]]
ContributorHi @JohnT_Intel
I am getting confused now !
2 different PFL User Guides with 2 different constraint suggestions! Which one is right ??
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
| flash_nce | set_false_path |
| flash_addr | set_false_path |
| flash_data | Normal read mode: set_false_path • Burst read mode: set_input_delay |
| fpga_data | set_output_delay |
| fpga_dclk | set_output_delay |
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https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html
1.4.2.1. Constraining Clock Signal
1.4.2.2. Constraining Synchronous input and Output ports
1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports
1.4.2.4. Summary of PFL Timing constraints
| flash_nce | set_max_delay -from pfl_clk -to <port> |
| flash_addr | set_max_delay -from pfl_clk -to <port> |
| flash_data |
|
| fpga_data | set_output_delay -clock fpga_dclk <port> |
| fpga_dclk |
|
