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Contributor

4 years ago

How to properly constrain the PFL for STA

Hi @JohnT_Intel FPGA_dclk output of the PFL (Parallel Flash Loader). FPGA_dclk is an output of the PFL and gets propagated to my top level wrapper output port. The FPGA_dclk is used normally to con...

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Regular Contributor

4 years ago

Hi,

Could you send to me through private message?

Knug
Contributor
4 years ago
Hi @JohnT_Intel

I generated another ticket with that and it was deleted again. It is important to get the constraints right. What is going on here ?

why there are differences in constraints between the 2 intel docs ??

How do I send a private message? & why my latest messages get deleted ?

What is your private email address ?

Not happy with this matter .
- Knug
  Contributor
  4 years ago
  Hi @JohnT_Intel
  
  I just sent it as a private message. Did you receive it?
  - Knug
    Contributor
    4 years ago
    Hi @JohnT_Intel
    
    Did you receive my private message?
    
    Another query here wrt constraints. Included this within the private message too.
    
    Hope I will receive a reply soon because we will have a review on this with my company later on today and I have to let them know.
    
    --
    
    Neither PFL document listed below lists what constrain to add to the flash_nreset output port of my combined PFL.
    
    I have enabled this extra pin in the PFL IP core & connected it to the reset pin of the flash memory device
    
    Is this pin an Asynchronous output? Can I declare to it ie ‘set_false_path -to flash_nreset’ ?
    
    Regards,
    
    Kevin