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FabriceNs's avatar
FabriceNs
Icon for New Contributor rankNew Contributor
53 minutes ago

Request about FPGA 10CL025YU256A7G

I wanted to ask you a question about the Altera 10CL025YU256A7G FPGA. We would like to implement a QSPI bus that could operate at a maximum frequency of 166 MHz in DDR mode and at a supply voltage of 3.3 V. In theory, the I/O pins of this FPGA should be able to operate at 200 MHz, so we believe this should be feasible:

 

However, when running simulations with the FPGA acting as the driver, we are encountering some limitations at a 3.3 V supply voltage.

 

While reviewing the FPGA's IBIS file, I noticed that for supply voltages below 3.3 V, the file provides several models that allow the drive strength and slew rate configurations to be adjusted. As an example, below are the available I/O models for a supply voltage of 1.8 V. The number following the letter 'd' indicates the current provided by the buffer (for example, d8 = 8 mA drive strength), while the letters at the end of the model indicate the slew-rate configuration ('s' = slow, 'm' = medium, 'f' = fast).

 ttl18_cio_d2
ttl18_cio_d4
ttl18_cio_d6
ttl18_cio_d8s
ttl18_cio_d10s
ttl18_cio_d12s
ttl18_cio_d16s
ttl18_cio_d8m
ttl18_cio_d10m
ttl18_cio_d12m
ttl18_cio_d16m
ttl18_cio_d8f
ttl18_cio_d10f
ttl18_cio_d12f
ttl18_cio_d16f

 

For a 3.3 V supply voltage, the IBIS file provides far fewer models. For TTL, there are two models, one with 4 mA drive strength and another with 8 mA, while for CMOS there is only one model with 2 mA drive strength:

ttl33_cio_d4
ttl33_cio_d8
cmos33_cio_d2

 

This brings me to my question: are there any limitations on the output buffers when operating at a 3.3 V supply voltage? If not, do you have a more complete IBIS file with additional drive-strength and slew-rate models?

 

What we are seeing in our simulations is that, at this supply voltage and a frequency of 166 MHz, the signal quality is somewhat poor from a signal-integrity perspective. The model that provides the best performance is ttl33_cio_d8, but we are seeing relatively slow rise/fall times (greater than 1 ns), which somewhat limits the maximum operating frequency.

 

At lower supply voltages, the availability of models with higher drive strengths results in faster signal transitions, and the signal integrity looks better at the frequency we are targeting.

Could you please confirm whether the 3.3 V I/O buffers have any inherent limitations in terms of drive strength or slew rate, and whether a more comprehensive IBIS model is available?

Thank you in advance for your help.

 

As additional information, I am attaching a screenshot of the DQS signal generated by the FPGA when operating at 120 MHz. As you can see, the signal already shows some degradation at this frequency:

 

 

 

 

I generated this signal using the TTL33_CIO_D8 model, which provides the best results among the models available for a 3.3 V supply voltage. The other models provided in the IBIS file for 3.3 V have lower drive strength, and the resulting signal is even worse (TTL33_CIO_D4 and CMOS33_CIO_D2).

 

As mentioned in my previous message, at lower supply voltages the IBIS file provides a wider range of models, including models with higher drive strength. This is the reason for our question: is the IBIS model for 3.3 V incomplete, or is there actually a limitation on the output buffer at this supply voltage?

 

Transceiver

1 Reply

  • ai_responder's avatar
    ai_responder
    Icon for Community Manager rankCommunity Manager
    49 minutes ago

    This is a real hardware limitation, not an incomplete IBIS file. Let me explain what the Cyclone 10 LP handbook documents for the 3.3 V I/O standards and why you're seeing exactly three models.

    Documented drive-strength options are genuinely limited at 3.3 V

    The Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook explicitly lists only the following current-strength settings for the 3.3 V standards:

    Your IBIS file (cmos33_cio_d2, ttl33_cio_d4, ttl33_cio_d8) maps exactly to these three documented settings — so the IBIS file is complete and accurate; there are no hidden higher-drive-strength 3.3 V models to be found.

    Compare this to lower-voltage standards, which have significantly more options:

    The underlying reason is the I/O transistor technology: the Cyclone 10 LP devices use TSMC 2.5 V transistor technology in the I/O buffers, though the devices are compatible with 2.5 V, 3.0 V, and 3.3 V configuration voltage standards. Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook Operating the I/O buffers at 3.3 V is at the ceiling of what these transistors support, which constrains both the number of drive-strength taps and maximum achievable output current.

    Slew-rate control is also not available at 3.3 V

    The slew-rate control table in the handbook covers 3.0 V LVTTL/LVCMOS and below — there is no 3.3 V LVTTL entry in that table. This explains why your 3.3 V IBIS models carry no slow/medium/fast suffix variants: programmable slew rate control is a supported feature for optimizing signal integrity, Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook but it is not available for the 3.3 V standards on this device.

    For reference, slew rate control is confirmed for:

    Practical implications for your 166 MHz DDR QSPI design

    The slow rise/fall times you are observing (>1 ns even at 120 MHz with ttl33_cio_d8) are a direct consequence of this hardware constraint: 8 mA is the maximum available drive strength at 3.3 V, and there is no fast-slew-rate option. Achieving clean signal integrity at 166 MHz DDR with this driver is going to be very challenging on anything but a very short, lightly loaded trace.

    My recommendation: if your QSPI flash device and board design can tolerate it, consider switching VCCIO to 2.5 V or 1.8 V. At 2.5 V you gain access to 16 mA drive with slew-rate control, and at 1.8 V you get up to 16 mA with slow/medium/fast slew-rate variants — exactly the richer model set you observed in the IBIS file. The current strength setting is what the output buffer is guaranteed to drive at the switching thresholds of the I/O standard — for example, a buffer with an 8 mA setting will drive at least 8 mA at the minimum VOH and maximum VOL for the standard. To verify the actual current for your specific board topology, running IBIS simulations is recommended. Does the current strength of an output buffer refer to the maximum current that the buffer is able to drive out?

    If 3.3 V is a hard requirement, your best path is board-level optimization: minimize trace length and loading, use matched termination to control reflections and reduce the effective slew-rate requirement on the driver, and validate carefully with IBIS simulation as the ttl33_cio_d8 model is the highest-fidelity option available for that voltage.


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    Thank you very much.