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FabriceNs's avatar
FabriceNs
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1 hour ago

Request about FPGA 10CL025YU256A7G

I wanted to ask you a question about the Altera 10CL025YU256A7G FPGA. We would like to implement a QSPI bus that could operate at a maximum frequency of 166 MHz in DDR mode and at a supply voltage of...
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ai_responder's avatar
ai_responder
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1 hour ago

This is a real hardware limitation, not an incomplete IBIS file. Let me explain what the Cyclone 10 LP handbook documents for the 3.3 V I/O standards and why you're seeing exactly three models.

Documented drive-strength options are genuinely limited at 3.3 V

The Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook explicitly lists only the following current-strength settings for the 3.3 V standards:

Your IBIS file (cmos33_cio_d2, ttl33_cio_d4, ttl33_cio_d8) maps exactly to these three documented settings — so the IBIS file is complete and accurate; there are no hidden higher-drive-strength 3.3 V models to be found.

Compare this to lower-voltage standards, which have significantly more options:

The underlying reason is the I/O transistor technology: the Cyclone 10 LP devices use TSMC 2.5 V transistor technology in the I/O buffers, though the devices are compatible with 2.5 V, 3.0 V, and 3.3 V configuration voltage standards. Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook Operating the I/O buffers at 3.3 V is at the ceiling of what these transistors support, which constrains both the number of drive-strength taps and maximum achievable output current.

Slew-rate control is also not available at 3.3 V

The slew-rate control table in the handbook covers 3.0 V LVTTL/LVCMOS and below — there is no 3.3 V LVTTL entry in that table. This explains why your 3.3 V IBIS models carry no slow/medium/fast suffix variants: programmable slew rate control is a supported feature for optimizing signal integrity, Cyclone 10 LP Core Fabric and General Purpose I/Os Handbook but it is not available for the 3.3 V standards on this device.

For reference, slew rate control is confirmed for:

Practical implications for your 166 MHz DDR QSPI design

The slow rise/fall times you are observing (>1 ns even at 120 MHz with ttl33_cio_d8) are a direct consequence of this hardware constraint: 8 mA is the maximum available drive strength at 3.3 V, and there is no fast-slew-rate option. Achieving clean signal integrity at 166 MHz DDR with this driver is going to be very challenging on anything but a very short, lightly loaded trace.

My recommendation: if your QSPI flash device and board design can tolerate it, consider switching VCCIO to 2.5 V or 1.8 V. At 2.5 V you gain access to 16 mA drive with slew-rate control, and at 1.8 V you get up to 16 mA with slow/medium/fast slew-rate variants — exactly the richer model set you observed in the IBIS file. The current strength setting is what the output buffer is guaranteed to drive at the switching thresholds of the I/O standard — for example, a buffer with an 8 mA setting will drive at least 8 mA at the minimum VOH and maximum VOL for the standard. To verify the actual current for your specific board topology, running IBIS simulations is recommended. Does the current strength of an output buffer refer to the maximum current that the buffer is able to drive out?

If 3.3 V is a hard requirement, your best path is board-level optimization: minimize trace length and loading, use matched termination to control reflections and reduce the effective slew-rate requirement on the driver, and validate carefully with IBIS simulation as the ttl33_cio_d8 model is the highest-fidelity option available for that voltage.


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Thank you very much.