[PCIE_DESIGN_EXAMPLE][AGILEX7][QUARTUS25.3.0] - failed at elaboration process

Question

Hello,I am trying to simulate with questa fe the pcie design example (with pipe mode for external dma controller) based on agilex7 generated with quartus pro 25.3.0 but i am facing these issues when i run this script under "pcie_ed_sim_tb/pcie_ed_sim_tb/sim/mentor" as follow : vsim -do run_msim.tcl# ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x16_l0) is not on a downward path.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x16_l0' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x16_l0.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x4_l12) is not on a downward path.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x4_l12' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x4_l12.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x4_l4) is not on a downward path.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x4_l4' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x4_l4.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Warning: (vsim-3008) [CNNODP] - Component name (i_pclk__x8_l8) is not on a downward path.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Error: (vsim-3043) Unresolved reference to 'i_pclk__x8_l8' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_pclk__x8_l8.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Warning: (vsim-3008) [CNNODP] - Component name (i_rxpipe0__dirfeedback) is not on a downward path.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Error: (vsim-3043) Unresolved reference to 'i_rxpipe0__dirfeedback' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_rxpipe0__dirfeedback.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Warning: (vsim-3008) [CNNODP] - Component name (i_rxpipe0__linkevaluationfeedbackfiguremerit) is not on a downward path.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589# ** Error: (vsim-3043) Unresolved reference to 'i_rxpipe0__linkevaluationfeedbackfiguremerit' in ftile_s20_v0__pcie__tile_0.z1577b.z1577b_inst.i_rxpipe0__linkevaluationfeedbackfiguremerit.# Time: 0 fs Iteration: 0 Instance: /pcie_ed_sim_tb/dut_pcie_tb_ip/dut_pcie_tb/tile File: ../../../../support_logic/pcie_ed_sim_auto_tiles.sv Line: 34589.....I also have followed the Altera recommendations :Note:&nbsp;Due to a problem in the&nbsp;Quartus® Prime Pro Edition&nbsp;Software version 25.3, you are required to add&nbsp;"-suppress 2732"&nbsp;to USER_DEFINED_COMPILE_OPTIONS and&nbsp;"-suppress 10000 "&nbsp;to USER_DEFINED_ELAB_OPTIONS in the&nbsp;run_msim.tcl&nbsp;simulation script manually for a successful simulation with the Questa simulator.But i am still facing these above issues.What can i do ?Regards,Frederic

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vent_altera · Answer

Hi Frederic,Thanks for reaching out.The suppress 2732/10000 workaround you applied addresses a separate, known issue with the F-Tile Multi Channel DMA IP simulation in Quartus Prime Pro 25.3 when using Riviera Pro or Siemens Questa*: https://community.altera.com/kb/knowledge-base/why-does-simulation-of-the-f-tile-multi-channel-dma-fpga-ip-for-pci-express-erro/338491The vsim-3008/vsim-3043 errors you are seeing are not targeted in this workaround.&nbsp;Could you please let me know if you are using F-Tile MCDMA IP, and which Questa FE simulator version? Additionally, could you disable the PIPE mode in your design example generation if your flow does not strictly require this mode?Note that, the Table 38.&nbsp;Supported Simulators for F-Tile MCDMA IP in https://docs.altera.com/r/docs/683517/25.3.1/multi-channel-dma-ip-for-pci-express-design-example-user-guide/supported-simulators MCDMA Design Example user guide confirms that the External Descriptor Controller Design Example (Data Mover Only mode) does not support Questa - Altera FPGA Edition and requires the full QuestaSIM instead. Please switch to the full QuestaSIM instead of Questa FE if you are using the F-Tile MCDMA IP. &nbsp;Thanks.Best Regards,Ven

vent_altera · Answer

Hi Frederic,Are there any updates on my previous message?Thanks.Best Regards,Ven

fgr1 · Answer

Hello and thanks Ven for answering to my issue.
Yes i confirm that we are using F-Tile MCDMA IP with Data Mover Only option.
I am using Questa Altera FE edition (associated to the Quartus Pro version 25.3.0).
I will try to remove the PIPE mode by using only serial simulation and will get you back soon.
Is there any chance to get a simulation with the above options (Data Mover Only) with a new quartus pro version ?

Regards,

Frederic

vent_altera · Answer

Hi Frederic,Thank you for the update.The Questa Altera FE edition simulator is unlikely to be supported for simulation of the&nbsp;Data Mover Only - External Descriptor Controller Example Design) in future Quartus version. It is recommended to use the full version of QuestaSim to run the simulation, which is supported in Quartus Prime Pro Edition v25.3.0. When using the full version of QuestaSim, you may enable the PIPE option to accelerate the simulation.Additionally, the vsim-3008 and vsim-3043 errors you encountered previously with PIPE mode enabled can be resolved by switching to the full version of QuestaSim. Please note that you may also need to apply the suppress 2732/10000 workaround described in the KDB (https://community.altera.com/kb/knowledge-base/why-does-simulation-of-the-f-tile-multi-channel-dma-fpga-ip-for-pci-express-erro/338491) before proceeding with the simulation.Thanks.Best Regards,Ven

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[PCIE_DESIGN_EXAMPLE][AGILEX7][QUARTUS25.3.0] - failed at elaboration process

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