Forum Discussion

Icon for Contributor rank

Contributor

5 years ago

How to properly constrain the PFL for STA

Hi @JohnT_Intel FPGA_dclk output of the PFL (Parallel Flash Loader). FPGA_dclk is an output of the PFL and gets propagated to my top level wrapper output port. The FPGA_dclk is used normally to con...

Icon for Contributor rank

Contributor

5 years ago

Hi @JohnT_Intel

I generated another ticket with that and it was deleted again. It is important to get the constraints right. What is going on here ?

why there are differences in constraints between the 2 intel docs ??

How do I send a private message? & why my latest messages get deleted ?

What is your private email address ?

Not happy with this matter .

Icon for Contributor rank

Contributor

5 years ago

Hi @JohnT_Intel

I just sent it as a private message. Did you receive it?