How to properly constrain the PFL for STA

Knug
Contributor
4 years ago
Hi @JohnT_Intel

That link you sent me lists set_output_delay on the fpga_dclk !

I noticed another doc that lists the fpga_dclk as a generated clk which I constrained.

I sent another message with the differences between the 2 docs which was confusing. Did you see this ?

This lists other PFL constraints too. It states false paths in one of them whereas set_max_delays in the other one. This is confusing. Which one is right?
- Knug
  Contributor
  4 years ago
  Hi @JohnT_Intel
  
  This is what I was talking about :
  
  2 different PFL User Guides with 2 different constraint suggestions! Which one is right ??
  
  https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
  
  flash_nce
  
  set_false_path
  
  flash_addr
  
  set_false_path
  
  flash_data
  
  Normal read mode:
  set_false_path
  • Burst read mode:
  set_input_delay
  
  fpga_data
  
  set_output_delay
  
  fpga_dclk
  
  set_output_delay
  
  -----
  
  https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html
  
  1.4.2.1. Constraining Clock Signal
  
  1.4.2.2. Constraining Synchronous input and Output ports
  
  1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports
  
  1.4.2.4. Summary of PFL Timing constraints
  
  flash_nce
  
  set_max_delay -from pfl_clk -to <port>
  
  flash_addr
  
  set_max_delay -from pfl_clk -to <port>
  
  flash_data
  
  Read mode (PFL to Flash ROM)
  
  set_max_delay -from <port> to pfl_clk
  
  Write mode (Flash ROM to PFL) set_false_path
  
  fpga_data
  
  set_output_delay -clock fpga_dclk <port>
  
  fpga_dclk
  
  Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>
- Knug
  Contributor
  4 years ago
  Hi @JohnT_Intel
  
  I just re-sent the doc differences and it was deleted by the moderator. Why ?
  - Knug
    Contributor
    4 years ago
    2 different PFL User Guides with 2 different constraint suggestions! Which one is right ??
    
    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_pfl.pdf
    
    flash_nce
    
    set_false_path
    
    flash_addr
    
    set_false_path
    
    flash_data
    
    Normal read mode:
    set_false_path
    • Burst read mode:
    set_input_delay
    
    fpga_data
    
    set_output_delay
    
    fpga_dclk
    
    set_output_delay
    
    -----
    
    https://www.intel.com/content/www/us/en/programmable/documentation/sss1411439280066.html
    
    1.4.2.1. Constraining Clock Signal
    
    1.4.2.2. Constraining Synchronous input and Output ports
    
    1.4.2.3. Constraining Asynchronous input and Output ports and Bidirectional Synchronous ports
    
    1.4.2.4. Summary of PFL Timing constraints
    
    flash_nce
    
    set_max_delay -from pfl_clk -to <port>
    
    flash_addr
    
    set_max_delay -from pfl_clk -to <port>
    
    flash_data
    
    Read mode (PFL to Flash ROM)
    
    set_max_delay -from <port> to pfl_clk
    
    Write mode (Flash ROM to PFL) set_false_path
    
    fpga_data
    
    set_output_delay -clock fpga_dclk <port>
    
    fpga_dclk
    
    Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>
  - Knug
    Contributor
    4 years ago
    Hi @JohnT_Intel
    
    I just re-sent again the doc differences and it was deleted again by the moderator. Why ?

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How to properly constrain the PFL for STA

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fpga_data	set_output_delay -clock fpga_dclk <port>
fpga_dclk		Input clock to DCLK ratio = 1 create_generated_clock -source pfl_clk -invert <fpga_dclk port>