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Contributor

4 years ago

How to properly constrain the PFL for STA

Hi @JohnT_Intel FPGA_dclk output of the PFL (Parallel Flash Loader). FPGA_dclk is an output of the PFL and gets propagated to my top level wrapper output port. The FPGA_dclk is used normally to con...

JohnT_Altera

Regular Contributor

4 years ago

Hi,

I have received and have reply to you.

Knug

Contributor

4 years ago

Hi @JohnT_Intel

My last 3 Messages to the private email got back :

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Forum Discussion

How to properly constrain the PFL for STA

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