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Knug's avatar
Knug
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4 years ago

How to properly constrain the PFL for STA

Hi @JohnT_Intel FPGA_dclk output of the PFL (Parallel Flash Loader). FPGA_dclk is an output of the PFL and gets propagated to my top level wrapper output port. The FPGA_dclk is used normally to con...
Knug's avatar
Knug
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4 years ago

Hi @JohnT_Intel

That kit constraints file looks wrong wrt the DCLK constraint. Please comment here.

Wrt the PFL FPGA IP User Guide document this needs to be constrained as a generated clock. I did this.

Reviewing the rest of my wrapper wrt PFL timing constraints.

It lists many false paths and set_max_delay ones for input/output asynchronous signals in the PFL IP user Guide.

If any issues will get back.

Regards,

Kevin