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Knug's avatar
Knug
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4 years ago

How to properly constrain the PFL for STA

Hi @JohnT_Intel FPGA_dclk output of the PFL (Parallel Flash Loader). FPGA_dclk is an output of the PFL and gets propagated to my top level wrapper output port. The FPGA_dclk is used normally to con...
JohnT_Altera's avatar
JohnT_Altera
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4 years ago

Hi,


Could you send to me through private message?


Knug's avatar
Knug
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4 years ago

Hi @JohnT_Intel

I generated another ticket with that and it was deleted again. It is important to get the constraints right. What is going on here ?

why there are differences in constraints between the 2 intel docs ??

How do I send a private message? & why my latest messages get deleted ?

What is your private email address ?

Not happy with this matter .

  • Knug's avatar
    Knug
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    4 years ago

    Hi @JohnT_Intel

    I just sent it as a private message. Did you receive it?

    • Knug's avatar
      Knug
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      4 years ago

      Hi @JohnT_Intel

      Did you receive my private message?

      Another query here wrt constraints. Included this within the private message too.

      Hope I will receive a reply soon because we will have a review on this with my company later on today and I have to let them know.

      --

      Neither PFL document listed below lists what constrain to add to the flash_nreset output port of my combined PFL.

      I have enabled this extra pin in the PFL IP core & connected it to the reset pin of the flash memory device

      Is this pin an Asynchronous output? Can I declare to it ie ‘set_false_path -to flash_nreset’ ?

      Regards,

      Kevin

      • Knug's avatar
        Knug
        Icon for Contributor rankContributor
        4 years ago

        Hi @JohnT_Intel

        Seen also JTAG signals not constrained.

        Timing STA analysis reported following unconstrained :

        • no output delay : altera_reserved_tdo
        • no input delays : altera_reserved_tms, altera_reserved_tck & alrera_reserved_tdi

        How do we constrain them ?

        Well editing the ticket now ...

        I tried constraining the above jtag signals using input / output delays BUT still see the other issue I have no_clocks reported which I can see its related to the loader Flash programming IP. They popped out 140 of them when I 'check_timing' using the Timing Analyser. Planning to raise a new ticket on this matter!

        Few 'Check Timing' No clock listed below :

        altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_pgm:pgm|custom_jtag_counter:jtag_addr|data_reg[0]
        altera_parallel_flash_loader_2:parallel_flash_loader_2_0|altera_pfl2_pgm:pgm|custom_jtag_counter:jtag_addr|data_reg[1]

        ::::

        sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][4]

        :::

        Many others, 140 in total ...

        My top level clock is defined ok. What internal generated clock I require here ?

        In the other ticket I will include all warnings seen if I can, or should I send them via private message ?