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rsing108's avatar
rsing108
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

can't program stratix 10 GX with pcie hard ip+ example design

I am getting the following errors while programming the Stratix 10 GX board with the PCIE hard ip+ example design.

quartus_pro 19.4

Error (18950): Device has stopped receiving configuration data
Error (18948): Error message received from device: Detected hardware access error. There is a failure in accessing external hardware. (Subcode 0x0032, Info 0x00000000, Location 0x0000CC00)
Error (20072): A PMBUS error has occurred during configuration. Potential errors: Incorrect VID setting in Quartus Project. The target device fails to communicate to smart regulator or PMBUS Master on board.

Why am I getting these errors as all vid settings are auto generated? How to solve these issues?

19 Replies

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    To better understanding the problem, could you please provide the following info?


    1. How do you generate the example design? Is this from the IP GUI?
    2. Did you connect the board to a proper setup, where there is PCIe reference clock coming to the FPGA end point?


    Regards -SK


  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Thanks for the reply.


    Did you connect the PCIe End point to the root port with the proper PCIe reference clock before you program the SOF? If without a proper PCIe reference clock, you will fail the programming.


    Regards -SK


    • rsing108's avatar
      rsing108
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi @SengKok_L_Intel ,

      I did not find any such step in the manual so I have not specifically defined it, but shouldn't it be already done while generating the example design? Also does this attachment help or should I provide any other file? Sorry, I am not much familiar with this IP.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    What I mean is, do you physically connect the development kit (Endpoint) with a Host PC (Rootport) when you program the FPGA?


    • rsing108's avatar
      rsing108
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi @SengKok_L_Intel

      The refclk pin is connected to PIN_AK41

      I am attaching the .qsf file for all the pin assignments and while generating the design I parameterized the port type as "native endpoint" and not "Root port".

    • rsing108's avatar
      rsing108
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Yes the device ID is 1SG280LN2F43E2VG and is placed in a server along with another exactly same card

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Are you using a custom board and this is not Intel FPGA development kit? I'm asking this is because, the device ID 1SG280LN2F43E2VG is not the same as Stratix 10 Development Kit at the link below:


    https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-fpga.html


    Other questions:

    1. Does the server is power up, and there is a valid PCIe clock sending from the server to FPGA when you program the FPGA?
    2. Do you able to program a simple design (without the PCIe)?


    Regards -SK




  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Hi,


    Can you send me your simple design 's QSF file that able to program successfully? I would like to have a look of the Power setting and see if there is any difference.


    Regards -SK


  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    From the vendor.qsf file, the PCIe reference clock is using T34, but you are using AK41. Could you please double check? Or perhaps you can get a simple PCIe design from Bittware?


    set_location_assignment PIN_T34 -to pcie_refclk


    Regards -SK


    • rsing108's avatar
      rsing108
      Icon for Occasional Contributor rankOccasional Contributor
      5 years ago

      Hi @SengKok_L_Intel ,

      I changed the refclk pin to the same as the vendor one and also changed the rest of the pins according the vendor's pin configuration. But there is still an error while programming the board:

      Error(18952): Error status: Device does not accept configuration request

      • rsing108's avatar
        rsing108
        Icon for Occasional Contributor rankOccasional Contributor
        5 years ago

        Hi @SengKok_L_Intel ,It seems I need to get the server rebooted first. I will update you once I get it rebooted.

  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

    Thank for the update. If this still can't work, probably you can request a simple design from Bittware that can work properly for reference. This is to ensure all the pin assignments and VID setting are correct.


    Regards -SK


  • SengKok_L_Intel's avatar
    SengKok_L_Intel
    Icon for Regular Contributor rankRegular Contributor
    5 years ago

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