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rsing108's avatar
rsing108
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

can't program stratix 10 GX with pcie hard ip+ example design

I am getting the following errors while programming the Stratix 10 GX board with the PCIE hard ip+ example design. quartus_pro 19.4 Error (18950): Device has stopped receiving configuration data ...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

What I mean is, do you physically connect the development kit (Endpoint) with a Host PC (Rootport) when you program the FPGA?


  • rsing108's avatar
    rsing108
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi @SengKok_L_Intel

    The refclk pin is connected to PIN_AK41

    I am attaching the .qsf file for all the pin assignments and while generating the design I parameterized the port type as "native endpoint" and not "Root port".