SengKok_L_IntelRegular ContributorJoined 7 years ago761 Posts32 LikesLikes received39 SolutionsView All Badges
ContributionsMost RecentMost LikesSolutionsRe: Cyclone 10GX: Do I need 100 MHz CLK_USR input with PCI Express? If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. Re: DK-DEV-10AX115S-A out of stock If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. Re: Cyclone V GX - HARD IP PCIe - Reference Clock If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. Re: Need support in Link analyzer tool If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. Re: PCIe LTSSM debug If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. Re: Cyclone 10GX: Do I need 100 MHz CLK_USR input with PCI Express? Hi, This is required to connect a free running clock for the CLKUSR. else the transceiver calibration cannot be started, and it will impact the PCIe. Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines Regards -SK Re: DK-DEV-10AX115S-A out of stock Hi, You may refer to the following Arria 10 development kit for more detail. Intel Arria 10 GX FPGA Development Kit Re: Cyclone V GX - HARD IP PCIe - Reference Clock Hi, Yes, this is unable to use the output of the PLL as the PCIe reference clock. Re: FIR II Data Type If further support is needed in this thread, please post a response within 15 days. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. Re: PCIe LTSSM debug Hi, Probably you can let us know what you see from the lspci command, the actual size of onchip memory that you connected to BARs, and also your expectation, so that we can assist you further. Thanks.